testsuite/synth: check ram in mem01 and mem02

4 files changed, 12 insertions, 8 deletions

diff --git a/testsuite/synth/mem02/ram3.vhdl b/testsuite/synth/mem02/ram3.vhdl
index d67667c3e..3988be036 100644
--- a/testsuite/synth/mem02/ram3.vhdl
+++ b/testsuite/synth/mem02/ram3.vhdl
@@ -21,5 +21,7 @@ begin
       mem(ra) <= wdat;
     end if;
   end process;
+
+  --  As MEM is read in a whole, this is not a RAM.
   val <= mem;
 end behav;
diff --git a/testsuite/synth/mem02/ram4.vhdl b/testsuite/synth/mem02/ram4.vhdl
index c397e44f1..c96208f7b 100644
--- a/testsuite/synth/mem02/ram4.vhdl
+++ b/testsuite/synth/mem02/ram4.vhdl
@@ -22,6 +22,7 @@ begin
   begin
     if rising_edge (clk) then
       if rst = '1' then
+        --  As MEM is written in a whole, this is not a RAM.
         mem <= init;
       end if;
       rdat <= mem((idx.idx+1) * 2 - 1 downto idx.idx * 2);
diff --git a/testsuite/synth/mem02/ram6.vhdl b/testsuite/synth/mem02/ram6.vhdl
index 621e7cc27..70eb21054 100644
--- a/testsuite/synth/mem02/ram6.vhdl
+++ b/testsuite/synth/mem02/ram6.vhdl
@@ -21,5 +21,7 @@ begin
       mem(ra) <= wdat;
     end if;
   end process;
+
+  --  As MEM is read in a whole, this is not a RAM
   val <= mem;
 end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index fd8a749c3..1250b3f39 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -2,15 +2,14 @@
 
 . ../../testenv.sh
 
-for t in dpram1 ram3 ram4 ram6; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
+for t in dpram1; do
+    synth_tb $t 2> $t.log
+    grep "found R" $t.log
+done
 
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t --ieee-asserts=disable-at-0
-    clean
+# Designs that doesn't create a RAM/ROM
+for t in ram3 ram4 ram6; do
+    synth_tb $t 2> $t.log
 done
 
 synth ram8.vhdl -e > syn_ram8.vhdl