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author | Tristan Gingold <tgingold@free.fr> | 2022-11-05 08:04:30 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-11-05 08:04:30 +0100 |
commit | 2d1df99bab33364489a674bd97a184ec6c2ca520 (patch) | |
tree | 0cecdf95fa426435156cd47bb7cedbc29b15c461 /testsuite/synth/mem02/dpram2.vhdl | |
parent | 391714eeecaaa43259a7b5ef56a2c910104978c0 (diff) | |
download | ghdl-2d1df99bab33364489a674bd97a184ec6c2ca520.tar.gz ghdl-2d1df99bab33364489a674bd97a184ec6c2ca520.tar.bz2 ghdl-2d1df99bab33364489a674bd97a184ec6c2ca520.zip |
testsuite/mem02: add more tests for RAM inference.
Diffstat (limited to 'testsuite/synth/mem02/dpram2.vhdl')
-rw-r--r-- | testsuite/synth/mem02/dpram2.vhdl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/mem02/dpram2.vhdl b/testsuite/synth/mem02/dpram2.vhdl new file mode 100644 index 000000000..d7e98d6b7 --- /dev/null +++ b/testsuite/synth/mem02/dpram2.vhdl @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dpram1 is + port (raddr : std_logic_vector (3 downto 0); + rdat : out std_logic_vector (7 downto 0); + waddr : std_logic_vector (3 downto 0); + wdat : std_logic_vector (7 downto 0); + clk : std_logic); +end dpram1; + +architecture behav of dpram1 is + subtype memtype is std_logic_vector (16 * 8 - 1 downto 0); + signal mem : memtype; +begin + process (clk) + variable ra : natural; + variable wa : natural; + variable rlo, rhi : natural; + begin + if rising_edge (clk) then + ra := to_integer(unsigned (raddr)); + rlo := ra * 8; + rhi := rlo + 7; + rdat <= mem (rhi downto rlo); + wa := to_integer(unsigned (waddr)); + mem (wa * 8 + 7 downto wa * 8) <= wdat; + end if; + end process; +end behav; |