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authorTristan Gingold <tgingold@free.fr>2021-06-21 07:43:55 +0200
committerTristan Gingold <tgingold@free.fr>2021-06-21 08:07:13 +0200
commit09e1764ea6dcf08aa77f8b6f5115caca9de44057 (patch)
treec66014ebe875cad6ed20c6b7de326dab30b16286 /testsuite/synth/mem01
parent6aaabbfc1716fffd7b7185d53e791e77400950d2 (diff)
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testsuite/synth: check ram in mem01 and mem02
Diffstat (limited to 'testsuite/synth/mem01')
-rwxr-xr-xtestsuite/synth/mem01/testsuite.sh10
1 files changed, 3 insertions, 7 deletions
diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh
index 186456831..00e9022a9 100755
--- a/testsuite/synth/mem01/testsuite.sh
+++ b/testsuite/synth/mem01/testsuite.sh
@@ -3,14 +3,10 @@
. ../../testenv.sh
for t in rom1 srom01 sram01 sram02 sram03 sram05 dpram1 dpram2 dpram3; do
- analyze $t.vhdl tb_$t.vhdl
- elab_simulate tb_$t
- clean
+ synth_tb $t 2> $t.log
- synth $t.vhdl -e $t > syn_$t.vhdl
- analyze syn_$t.vhdl tb_$t.vhdl
- elab_simulate tb_$t --ieee-asserts=disable-at-0
- clean
+ # Each design has either a RAM or a ROM
+ grep 'found R' $t.log
done
echo "Test successful"