testsuite/synth: add latch01

3 files changed, 57 insertions, 0 deletions

diff --git a/testsuite/synth/latch01/latch01.vhdl b/testsuite/synth/latch01/latch01.vhdl
new file mode 100644
index 000000000..fc31d3cb1
--- /dev/null
+++ b/testsuite/synth/latch01/latch01.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity latch01 is
+  port (q : out std_logic;
+        d : std_logic;
+        en : std_logic);
+end latch01;
+
+architecture behav of latch01 is
+begin
+  process (en, d) is
+  begin
+    if en = '1' then
+      q <= d;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/latch01/tb_latch01.vhdl b/testsuite/synth/latch01/tb_latch01.vhdl
new file mode 100644
index 000000000..c1bd43e98
--- /dev/null
+++ b/testsuite/synth/latch01/tb_latch01.vhdl
@@ -0,0 +1,28 @@
+entity tb_latch01 is
+end tb_latch01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_latch01 is
+  signal q : std_logic;
+  signal d : std_logic;
+  signal en : std_logic;
+begin
+  dut: entity work.latch01
+    port map (q, d, en);
+
+  process
+    constant dv : std_logic_vector := b"010011";
+    constant ev : std_logic_vector := b"110101";
+    constant qv : std_logic_vector := b"011001";
+  begin
+    for i in dv'range loop
+      d <= dv (i);
+      en <= ev (i);
+      wait for 1 ns;
+      assert q = qv(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/latch01/testsuite.sh b/testsuite/synth/latch01/testsuite.sh
new file mode 100755
index 000000000..fb617b23a
--- /dev/null
+++ b/testsuite/synth/latch01/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_SYNTH_FLAGS=--latches
+
+for t in latch01; do
+    synth_tb $t
+done
+
+echo "Test successful"