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authorTristan Gingold <tgingold@free.fr>2019-10-08 06:28:45 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-08 06:28:45 +0200
commit14ba70a30d5ce4395eea8c668bcafc85790b5247 (patch)
tree573ed287f0e71e10c11de0758517a39d4a9c55b5 /testsuite/synth/issue964/tb_ent.vhdl
parent5c029fecafa67b4d47ce904a9ce8c52a07e479f7 (diff)
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testsuite/synth: add testcase for #964
Diffstat (limited to 'testsuite/synth/issue964/tb_ent.vhdl')
-rw-r--r--testsuite/synth/issue964/tb_ent.vhdl55
1 files changed, 55 insertions, 0 deletions
diff --git a/testsuite/synth/issue964/tb_ent.vhdl b/testsuite/synth/issue964/tb_ent.vhdl
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+++ b/testsuite/synth/issue964/tb_ent.vhdl
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+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+ signal clk : std_logic;
+ signal dout : std_logic;
+ signal enable : std_logic;
+ signal reset : std_logic;
+begin
+ dut: entity work.ent
+ port map (
+ enable => enable,
+ reset => reset,
+ q => dout,
+ clk => clk);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ enable <= '1';
+ reset <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ enable <= '1';
+ reset <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ pulse;
+ assert dout = '0' severity failure;
+
+ pulse;
+ assert dout = '1' severity failure;
+
+ enable <= '0';
+ pulse;
+ assert dout = '1' severity failure;
+
+ enable <= '1';
+ pulse;
+ assert dout = '0' severity failure;
+
+ wait;
+ end process;
+end behav;