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author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:58:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:58:35 +0200 |
commit | 88d594c84f6b07f312f9fa0a2c2403b81d9ca35d (patch) | |
tree | fd8b7b22f145c1d5660f1123cd9579451e1b4256 /testsuite/synth/issue953/ent.vhdl | |
parent | 9aeab4488aef1a576d648ce2a14d3bc3a893f1e6 (diff) | |
download | ghdl-88d594c84f6b07f312f9fa0a2c2403b81d9ca35d.tar.gz ghdl-88d594c84f6b07f312f9fa0a2c2403b81d9ca35d.tar.bz2 ghdl-88d594c84f6b07f312f9fa0a2c2403b81d9ca35d.zip |
testsuite/synth: add testcase for #953
Diffstat (limited to 'testsuite/synth/issue953/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue953/ent.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/issue953/ent.vhdl b/testsuite/synth/issue953/ent.vhdl new file mode 100644 index 000000000..72c7988b2 --- /dev/null +++ b/testsuite/synth/issue953/ent.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all, + ieee.numeric_std.all; + +entity ent is +end; + +architecture a of ent is + signal x : unsigned(7 downto 0); + signal y : unsigned(7 downto 0) := x / 2; + signal z : unsigned(15 downto 0) := x * 2; +begin +end; |