testsuite/synth: add testcase for #951

3 files changed, 87 insertions, 0 deletions

diff --git a/testsuite/synth/issue951/ent.vhdl b/testsuite/synth/issue951/ent.vhdl
new file mode 100644
index 000000000..1d6ae9a72
--- /dev/null
+++ b/testsuite/synth/issue951/ent.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+    port (
+        clk : in std_logic;
+        enable : in std_logic;
+        i : in std_logic;
+        o : out std_logic
+    );
+end;
+
+architecture a of ent is
+begin
+    process(clk)
+    begin
+        -- works:
+        --if rising_edge(clk) and enable = '1' then
+        if enable = '1' and rising_edge(clk) then
+            o <= i;
+        end if;
+    end process;
+end;
diff --git a/testsuite/synth/issue951/tb_ent.vhdl b/testsuite/synth/issue951/tb_ent.vhdl
new file mode 100644
index 000000000..a6a752054
--- /dev/null
+++ b/testsuite/synth/issue951/tb_ent.vhdl
@@ -0,0 +1,48 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal clk : std_logic;
+  signal en : std_logic;
+  signal din : std_logic;
+  signal dout : std_logic;
+begin
+  dut: entity work.ent
+    port map (clk => clk, enable => en, i => din, o => dout);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    din <= '0';
+    en <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+
+    din <= '1';
+    en <= '1';
+    pulse;
+    assert dout = '1' severity failure;
+
+    din <= '0';
+    en <= '0';
+    pulse;
+    assert dout = '1' severity failure;
+    wait;
+
+    din <= '0';
+    en <= '1';
+    pulse;
+    assert dout = '0' severity failure;
+    wait;
+
+  end process;
+end behav;
diff --git a/testsuite/synth/issue951/testsuite.sh b/testsuite/synth/issue951/testsuite.sh
new file mode 100755
index 000000000..0851b975a
--- /dev/null
+++ b/testsuite/synth/issue951/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"