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author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 07:37:54 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 07:37:54 +0200 |
commit | aefa14ad88fe7ea4621c6b3a3468432ae76b48cb (patch) | |
tree | c69c825871530dff6606b9b0c2f74dea96ed3d21 /testsuite/synth/issue947/ent.vhdl | |
parent | bf30078cae1fd5631c3ab8a19dfa6693aeb2c94b (diff) | |
download | ghdl-aefa14ad88fe7ea4621c6b3a3468432ae76b48cb.tar.gz ghdl-aefa14ad88fe7ea4621c6b3a3468432ae76b48cb.tar.bz2 ghdl-aefa14ad88fe7ea4621c6b3a3468432ae76b48cb.zip |
testsuite/synth: add testcase for #947
Diffstat (limited to 'testsuite/synth/issue947/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue947/ent.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue947/ent.vhdl b/testsuite/synth/issue947/ent.vhdl new file mode 100644 index 000000000..e32c700b5 --- /dev/null +++ b/testsuite/synth/issue947/ent.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + i : in bit; + o : out bit + ); +end; + +architecture a of ent is + signal test : std_logic_vector(7 downto 0); +begin + process(i) + begin + if test = "0" then + end if; + + o <= i; + end process; +end; |