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author | T. Meissner <programming@goodcleanfun.de> | 2021-02-09 07:31:00 +0100 |
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committer | GitHub <noreply@github.com> | 2021-02-09 07:31:00 +0100 |
commit | 7d5bfac5526528e32f5f44b9bea0bbdfee21a589 (patch) | |
tree | a3d749912cca5d83f8cb1da304b90a62713d2d59 /testsuite/synth/issue662/tb_psl_onehot.vhdl | |
parent | a75c135b5bb3c817ff0d9605c5cfabbfa721c13b (diff) | |
download | ghdl-7d5bfac5526528e32f5f44b9bea0bbdfee21a589.tar.gz ghdl-7d5bfac5526528e32f5f44b9bea0bbdfee21a589.tar.bz2 ghdl-7d5bfac5526528e32f5f44b9bea0bbdfee21a589.zip |
Add support for PSL onehot/onehot0 functions (#1633)
* vhdl: parse PSL onehot/onehot0 builtin calls. For #662
* update pyGHDL bindings
* Synthesis of PSL built-in onehot/onehot0 function.
* testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662
* doc: add info about PSL built-in functions onehot()/onehot0() for #662
* synth: refactor synthesis of onehot/onehot0 functions
Co-authored-by: eine <eine@users.noreply.github.com>
Diffstat (limited to 'testsuite/synth/issue662/tb_psl_onehot.vhdl')
-rw-r--r-- | testsuite/synth/issue662/tb_psl_onehot.vhdl | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/tb_psl_onehot.vhdl b/testsuite/synth/issue662/tb_psl_onehot.vhdl new file mode 100644 index 000000000..10b5d8c73 --- /dev/null +++ b/testsuite/synth/issue662/tb_psl_onehot.vhdl @@ -0,0 +1,69 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity tb_psl_onehot is +end entity tb_psl_onehot; + + +architecture psl of tb_psl_onehot is + + procedure seq (s : string; signal clk : std_logic; signal o : out std_logic) + is + begin + for i in s'range loop + wait until rising_edge(clk); + case s(i) is + when '0' | '_' => o <= '0'; + when '1' | '-' => o <= '1'; + when others => o <= 'X'; + end case; + end loop; + wait; + end seq; + + procedure hseq (s : string; signal clk : std_logic; signal o : out std_logic_vector(3 downto 0)) + is + begin + for i in s'range loop + wait until rising_edge(clk); + case s(i) is + when '0' | '_' => o <= x"0"; + when '1' => o <= x"1"; + when '2' => o <= x"2"; + when '3' => o <= x"3"; + when '4' => o <= x"4"; + when '5' => o <= x"5"; + when '6' => o <= x"6"; + when '7' => o <= x"7"; + when '8' => o <= x"8"; + when '9' => o <= x"9"; + when 'a' | 'A' => o <= x"A"; + when 'b' | 'B' => o <= x"B"; + when 'c' | 'C' => o <= x"C"; + when 'd' | 'D' => o <= x"D"; + when 'e' | 'E' => o <= x"E"; + when 'f' | 'F' | '-' => o <= x"F"; + when others => o <= x"X"; + end case; + end loop; + wait; + end hseq; + + signal a, b : std_logic_vector(3 downto 0) := x"0"; + signal c : natural range 0 to 15 := 0; + signal clk : std_logic := '1'; + +begin + + dut: entity work.psl_onehot port map (clk, a, b, c); + + clk <= not clk after 500 ps; + + -- 012345678901234 + SEQ_A : hseq ("111222444888888", clk, a); + SEQ_B : hseq ("111222444888999", clk, b); + + c <= to_integer(unsigned(b)); + +end architecture psl; |