Merge branch 'ghdl:master' into paebbels/pyGHDL-updates

1 files changed, 42 insertions, 0 deletions

diff --git a/testsuite/synth/issue412/generic_pkg.vhdl b/testsuite/synth/issue412/generic_pkg.vhdl
new file mode 100644
index 000000000..3a97c2961
--- /dev/null
+++ b/testsuite/synth/issue412/generic_pkg.vhdl
@@ -0,0 +1,42 @@
+-- package containing a type-generic D Flip Flop
+-- may not be 100% valid VHDL code, contact ktbarrett on gitter
+-- non-generic version does synthesize correctly
+package generic_pkg is
+
+  procedure generic_FF
+    generic (
+      constant T: type)
+    paramater (
+      signal   q    : out T;
+      signal   d    : in T;
+      signal   clk  : in std_logic;
+      signal   rst  : in std_logic;
+      constant INIT : in T;
+      signal   en   : in std_logic := '1');
+
+end package generic_pkg;
+  
+package body generic_pkg is
+  
+  procedure generic_FF
+    generic (
+      constant T: type)
+    paramater (
+      signal   q    : out T;
+      signal   d    : in T;
+      signal   clk  : in std_logic;
+      signal   rst  : in std_logic;
+      constant INIT : in T;
+      signal   en   : in std_logic := '1')
+    is
+  begin
+    if (rising_edge(clk)) then
+      if (rst /= '0') then
+        q <= INIT;
+      elsif (en = '1') then
+        q <= d;
+      end if;
+    end if;
+  end procedure generic_FF;
+      
+end package body generic_pkg;