testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

3 files changed, 0 insertions, 73 deletions

diff --git a/testsuite/synth/issue33/int_test.vhdl b/testsuite/synth/issue33/int_test.vhdl
deleted file mode 100644
index 62ea65bda..000000000
--- a/testsuite/synth/issue33/int_test.vhdl
+++ /dev/null
@@ -1,31 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-
-entity int_test is
-  generic (
-    INT_MIN : integer range 1 to 8 := 1;
-    INT_MAX : integer range 1 to 8 := 8
-  );
-  port (
-    clk : in std_logic;
-    a : in integer range INT_MIN to INT_MAX;
-    b : out integer range INT_MIN to INT_MAX
-  );
-end int_test;
-
-architecture rtl of int_test is
-  signal int : integer range INT_MIN to INT_MAX;
-begin
-  process (clk)
-  begin
-    if rising_edge (clk) then
-      if a < INT_MAX then
-        int <= a + 1;
-      else
-        int <= INT_MIN;
-      end if;
-    end if;
-  end process;
-  b <= int;
-end rtl;
-
diff --git a/testsuite/synth/issue33/int_test2.vhdl b/testsuite/synth/issue33/int_test2.vhdl
deleted file mode 100644
index eb43306c4..000000000
--- a/testsuite/synth/issue33/int_test2.vhdl
+++ /dev/null
@@ -1,31 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-
-entity int_test2 is
-  generic (
-    INT_MIN : integer range 1 to 8 := 1;
-    INT_MAX : integer range 1 to 8 := 8
-  );
-  port (
-    clk : in std_logic;
-    a : in integer range INT_MIN to INT_MAX;
-    b : out integer range INT_MIN to INT_MAX
-  );
-end int_test2;
-
-architecture rtl of int_test2 is
-  signal int : integer range INT_MIN to INT_MAX;
-begin
-  process (clk)
-  begin
-    if rising_edge (clk) then
-      if a < INT_MAX then
-        int <= a + 1;
-      else
-        int <= INT_MIN * 2;
-      end if;
-    end if;
-  end process;
-  b <= int;
-end rtl;
-
diff --git a/testsuite/synth/issue33/testsuite.sh b/testsuite/synth/issue33/testsuite.sh
deleted file mode 100755
index fca6f7d69..000000000
--- a/testsuite/synth/issue33/testsuite.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#! /bin/sh
-
-. ../../testenv.sh
-
-for t in int_test int_test2; do
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl
-    clean
-done
-
-echo "Test successful"