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| author | Tristan Gingold <tgingold@free.fr> | 2022-12-18 08:35:43 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2022-12-18 08:36:15 +0100 |
| commit | b4f09236ad974a133318d17a8487b36ebc35a78c (patch) | |
| tree | a2d61d7039219d334b60d61946705c2d63de8264 /testsuite/synth/issue2273/addsub_ovcy_.vhd | |
| parent | 36c276363fa35f6856bbd44e7a37e712aaab2a1e (diff) | |
| download | ghdl-b4f09236ad974a133318d17a8487b36ebc35a78c.tar.gz ghdl-b4f09236ad974a133318d17a8487b36ebc35a78c.tar.bz2 ghdl-b4f09236ad974a133318d17a8487b36ebc35a78c.zip | |
testsuite/synth: add a test for #2273
Diffstat (limited to 'testsuite/synth/issue2273/addsub_ovcy_.vhd')
| -rw-r--r-- | testsuite/synth/issue2273/addsub_ovcy_.vhd | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/testsuite/synth/issue2273/addsub_ovcy_.vhd b/testsuite/synth/issue2273/addsub_ovcy_.vhd new file mode 100644 index 000000000..8b9d0314a --- /dev/null +++ b/testsuite/synth/issue2273/addsub_ovcy_.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------- +-- -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- XX XX X X X X X X X XX -- +-- X X X X X X X X X X X X -- +-- X X X X X X X X X X X X -- +-- X X X X XXXXXX X X XXXXXX X -- +-- X X X X X X X X X -- +-- X X X X X X X X X -- +-- X X X X X X X X X X -- +-- X X XXXXXX XXXXXX XXXXXX XXXXXX X -- +-- -- +-- -- +-- O R E G A N O S Y S T E M S -- +-- -- +-- Design & Consulting -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- Web: http://www.oregano.at/ -- +-- -- +-- Contact: mc8051@oregano.at -- +-- -- +------------------------------------------------------------------------------- +-- -- +-- MC8051 - VHDL 8051 Microcontroller IP Core -- +-- Copyright (C) 2001 OREGANO SYSTEMS -- +-- -- +-- This library is free software; you can redistribute it and/or -- +-- modify it under the terms of the GNU Lesser General Public -- +-- License as published by the Free Software Foundation; either -- +-- version 2.1 of the License, or (at your option) any later version. -- +-- -- +-- This library is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- +-- Lesser General Public License for more details. -- +-- -- +-- Full details of the license can be found in the file LGPL.TXT. -- +-- -- +-- You should have received a copy of the GNU Lesser General Public -- +-- License along with this library; if not, write to the Free Software -- +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- +-- -- +------------------------------------------------------------------------------- +-- +-- +-- Author: Roland Höller +-- +-- Filename: addsub_ovcy_.vhd +-- +-- Date of Creation: Mon Aug 9 12:14:48 1999 +-- +-- Version: $Revision: 1.4 $ +-- +-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $ +-- +-- +-- Description: Adder/Subtractor with carry/borrow and arbitrary data +-- width and overflow flag. +-- +-- +-- +-- +------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +-----------------------------ENTITY DECLARATION-------------------------------- + +entity addsub_ovcy is + + generic (DWIDTH : integer := 4); + + port (opa_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand A + opb_i : in std_logic_vector(DWIDTH-1 downto 0); -- Operand B + addsub_i : in std_logic; -- Add or subtract command + cy_i : in std_logic; -- Carry input + cy_o : out std_logic; -- Carry/borrow bit + ov_o : out std_logic; -- Overflow flag + rslt_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Result + +end addsub_ovcy; + |