Fix issue #2126, add handling of to_ux01 to synthesis

2 files changed, 28 insertions, 0 deletions

diff --git a/testsuite/synth/issue2126/test.vhdl b/testsuite/synth/issue2126/test.vhdl
new file mode 100644
index 000000000..63de3d0df
--- /dev/null
+++ b/testsuite/synth/issue2126/test.vhdl
@@ -0,0 +1,19 @@
+-- Title      : Testcase for to_ux01 on a std_logic
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity test is
+
+  port (
+    sig_in : in std_logic_vector(1 downto 0);
+    sig_out : out std_logic;
+    sig_out_vec : out std_logic_vector(1 downto 0));
+end entity test;
+
+architecture str of test is
+
+begin  -- architecture str
+  sig_out <= to_ux01(sig_in(0)) and to_ux01(sig_in(1));
+  sig_out_vec <= to_ux01(sig_in);
+end architecture str;
diff --git a/testsuite/synth/issue2126/testsuite.sh b/testsuite/synth/issue2126/testsuite.sh
new file mode 100755
index 000000000..75ca5f68d
--- /dev/null
+++ b/testsuite/synth/issue2126/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth_only test
+
+echo "Test successful"