testsuite/synth: add a test for #2092

1 files changed, 25 insertions, 0 deletions

diff --git a/testsuite/synth/issue2092/testcase.vhdl b/testsuite/synth/issue2092/testcase.vhdl
new file mode 100644
index 000000000..a2659bad2
--- /dev/null
+++ b/testsuite/synth/issue2092/testcase.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+    port(
+        rst : in std_ulogic;
+        clk : in std_ulogic
+    );
+end entity testcase;
+
+architecture rtl of testcase is
+
+    component testcase2 port (
+        rst : in std_ulogic;
+        clk : in std_ulogic
+    );
+    end component;
+
+begin
+    testcase2_0: testcase2
+        port map (
+            clk => clk,
+            rst => rst
+        );
+end architecture rtl;