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authorTristan Gingold <tgingold@free.fr>2022-06-05 12:19:10 +0200
committerTristan Gingold <tgingold@free.fr>2022-06-05 12:19:10 +0200
commit16b5e35e7c9d872d6e5c5ee6b63cadc945057142 (patch)
tree6b31b5d8d02437196f53f69ef02380bc705f948d /testsuite/synth/issue2074
parent137641dbb2cf2900aea2da2ae90b9b4dfdc2bd5e (diff)
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testsuite/synth: add a test for #2074
Diffstat (limited to 'testsuite/synth/issue2074')
-rw-r--r--testsuite/synth/issue2074/bitvec.vhdl16
-rwxr-xr-xtestsuite/synth/issue2074/testsuite.sh9
2 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue2074/bitvec.vhdl b/testsuite/synth/issue2074/bitvec.vhdl
new file mode 100644
index 000000000..abd0786e3
--- /dev/null
+++ b/testsuite/synth/issue2074/bitvec.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity bitvec is
+port (
+ clk : in std_logic;
+ d : in bit_vector(7 downto 0);
+ q : out bit_vector(7 downto 0)
+);
+end entity;
+
+architecture rtl of bitvec is
+ constant a : bit_vector(7 downto 0) := X"5a";
+begin
+ q <= d and a;
+end architecture;
diff --git a/testsuite/synth/issue2074/testsuite.sh b/testsuite/synth/issue2074/testsuite.sh
new file mode 100755
index 000000000..27ce42d50
--- /dev/null
+++ b/testsuite/synth/issue2074/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only bitvec
+
+clean
+
+echo "Test successful"