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author | Tristan Gingold <tgingold@free.fr> | 2022-04-28 07:30:40 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-04-28 07:30:40 +0200 |
commit | 496dd0adacabcad79146f7beadefc9e938f8ef9f (patch) | |
tree | 6d5e45ec96d77c8b5db8685e5520c94c010918eb /testsuite/synth/issue2043/tb_ent1.vhdl | |
parent | 480b62181dd3e7d9e598de5672e1aa471d9355f9 (diff) | |
download | ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.tar.gz ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.tar.bz2 ghdl-496dd0adacabcad79146f7beadefc9e938f8ef9f.zip |
testsuite/synth: add a test for #2043
Diffstat (limited to 'testsuite/synth/issue2043/tb_ent1.vhdl')
-rw-r--r-- | testsuite/synth/issue2043/tb_ent1.vhdl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/issue2043/tb_ent1.vhdl b/testsuite/synth/issue2043/tb_ent1.vhdl new file mode 100644 index 000000000..80174e4dc --- /dev/null +++ b/testsuite/synth/issue2043/tb_ent1.vhdl @@ -0,0 +1,39 @@ +entity tb_ent1 is +end tb_ent1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent1 is + signal clk, rst : std_logic; + signal inp : std_logic_vector(15 downto 0); + signal data : std_logic_vector(63 downto 0); +begin + dut: entity work.ent1 + port map (clk, rst, inp, data); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + rst <= '1'; + pulse; + + rst <= '0'; + inp <= x"a001"; + pulse; + inp <= x"b002"; + pulse; + inp <= x"c003"; + pulse; + inp <= x"d004"; + pulse; + assert data = x"d004c003b002a001" severity failure; + wait; + end process; +end behav; |