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authorTristan Gingold <tgingold@free.fr>2022-02-22 20:59:31 +0100
committerTristan Gingold <tgingold@free.fr>2022-02-22 20:59:31 +0100
commit1325d61a595f90239a93e90c930c9bcbd725d3b3 (patch)
tree0d15103197793c95e887363b950d7ce4644d48b0 /testsuite/synth/issue1961/bug.vhdl
parent7526637883e495d3c8656602075db4d641747b73 (diff)
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testsuite/synth: add a test for #1961
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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+ port (
+ clk : in std_ulogic
+ );
+end bug;
+
+architecture struct of bug is
+
+ type a_t is record
+ value : unsigned;
+ end record;
+
+ type a_array_t is array(natural range<>) of a_t;
+
+ type b_t is record
+ a : a_array_t;
+ end record;
+
+ type b_array_t is array(natural range<>) of b_t;
+
+ function fun return natural is
+ variable b : b_array_t(0 to 1)(a(0 to 31)(value(31 downto 0)));
+ begin
+ return 0;
+ end function;
+
+ constant dummy : natural := fun;
+begin
+
+end architecture;