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author | Tristan Gingold <tgingold@free.fr> | 2022-01-11 19:39:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-01-12 08:30:18 +0100 |
commit | 4b97bbb1830f10ec17e07c5d312e35a83019a9ce (patch) | |
tree | 1fcf531958528e80bd6403b25a59c168aec87e83 /testsuite/synth/issue1945/tb_alias01.vhdl | |
parent | 82bc056875df996138ffa54b89f52663dfb17f1a (diff) | |
download | ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.gz ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.tar.bz2 ghdl-4b97bbb1830f10ec17e07c5d312e35a83019a9ce.zip |
testsuite/synth: add a test for #1945
Diffstat (limited to 'testsuite/synth/issue1945/tb_alias01.vhdl')
-rw-r--r-- | testsuite/synth/issue1945/tb_alias01.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue1945/tb_alias01.vhdl b/testsuite/synth/issue1945/tb_alias01.vhdl new file mode 100644 index 000000000..905a67a48 --- /dev/null +++ b/testsuite/synth/issue1945/tb_alias01.vhdl @@ -0,0 +1,26 @@ +entity tb_alias01 is +end tb_alias01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_alias01 is + signal i : std_logic_vector(7 downto 0); + signal o : std_logic; +begin + dut: entity work.alias01 + port map (i, o); + + process + begin + i <= "11000011"; + wait for 1 ns; + assert o = '1' severity failure; + + i <= "11100011"; + wait for 1 ns; + assert o = '0' severity failure; + + wait; + end process; +end behav; |