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| author | Tristan Gingold <tgingold@free.fr> | 2020-07-25 19:09:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-07-25 19:09:58 +0200 |
| commit | 092e788d5e00c034593d700859c001a43809038e (patch) | |
| tree | 5427e47d9a59e4025b4426a24d09508d6686c9bc /testsuite/synth/issue1406/repro2.vhdl | |
| parent | 9f2f749c32d6ca8500f3f96977a4ee3801dc13a2 (diff) | |
| download | ghdl-092e788d5e00c034593d700859c001a43809038e.tar.gz ghdl-092e788d5e00c034593d700859c001a43809038e.tar.bz2 ghdl-092e788d5e00c034593d700859c001a43809038e.zip | |
testsuite/synth: add tests for #1406
Diffstat (limited to 'testsuite/synth/issue1406/repro2.vhdl')
| -rw-r--r-- | testsuite/synth/issue1406/repro2.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/issue1406/repro2.vhdl b/testsuite/synth/issue1406/repro2.vhdl new file mode 100644 index 000000000..4f5f95b61 --- /dev/null +++ b/testsuite/synth/issue1406/repro2.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is + port (a, b : std_ulogic; + o : out std_ulogic); +end; + +architecture behav of repro is + type table_2d is array (std_ulogic, std_ulogic) of std_ulogic; + + constant and_table : table_2d := + -- UX01ZWLH- + ("UU0UUU0UU", -- U + "UX0XXX0XX", -- X + "000000000", -- 0 + "UX01XX01X", -- 1 + "UX0XXX0XX", -- Z + "UX0XXX0XX", -- W + "000000000", -- L + "UX01XX01X", -- H + "UX0XXX0XX" -- - + ); +begin + o <= and_table(a,b); +end; + |