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author | Tristan Gingold <tgingold@free.fr> | 2020-07-25 19:09:58 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-07-25 19:09:58 +0200 |
commit | 092e788d5e00c034593d700859c001a43809038e (patch) | |
tree | 5427e47d9a59e4025b4426a24d09508d6686c9bc /testsuite/synth/issue1406/half_adder.vhdl | |
parent | 9f2f749c32d6ca8500f3f96977a4ee3801dc13a2 (diff) | |
download | ghdl-092e788d5e00c034593d700859c001a43809038e.tar.gz ghdl-092e788d5e00c034593d700859c001a43809038e.tar.bz2 ghdl-092e788d5e00c034593d700859c001a43809038e.zip |
testsuite/synth: add tests for #1406
Diffstat (limited to 'testsuite/synth/issue1406/half_adder.vhdl')
-rw-r--r-- | testsuite/synth/issue1406/half_adder.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/issue1406/half_adder.vhdl b/testsuite/synth/issue1406/half_adder.vhdl new file mode 100644 index 000000000..4a6047ed4 --- /dev/null +++ b/testsuite/synth/issue1406/half_adder.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity half_adder is + port ( + clk_in : in std_logic; + n_rst_in : in std_logic; + a_in : in std_logic; + b_in : in std_logic; + c_out : out std_logic; + s_out : out std_logic + ); +end half_adder; + +architecture rtl of half_adder is +begin + reg_proc : process(clk_in, n_rst_in) + begin + if n_rst_in = '0' then + c_out <= '0'; + s_out <= '0'; + elsif rising_edge(clk_in) then + c_out <= a_in and b_in; + s_out <= a_in xor b_in; + end if; + end process reg_proc; +end rtl; |