testsuite/synth: add test for #1366

1 files changed, 30 insertions, 0 deletions

diff --git a/testsuite/synth/issue1366/issue_psl.vhdl b/testsuite/synth/issue1366/issue_psl.vhdl
new file mode 100644
index 000000000..99ce6fbbf
--- /dev/null
+++ b/testsuite/synth/issue1366/issue_psl.vhdl
@@ -0,0 +1,30 @@
+vunit issue_vunit (issue(psl)) {
+  
+  -- VHDL declaration seem to be working
+  signal a_delayed : std_logic := '0';
+
+  -- Other VHDL code not
+  -- results in parser errors
+  -- during synthesis
+  process is
+  begin
+    wait until rising_edge(clk);
+    a_delayed <= a;
+  end process;  
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  CHECK_a : assert always (a -> b);
+
+  -- You can't do anything with the declared signal
+  -- Can be synthesized with GHDL, however
+  -- results in error in ghdl-yosys-plugin:
+  -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:172
+  assert always a_delayed = prev(a);
+
+}
+
+