diff options
author | Tristan Gingold <tgingold@free.fr> | 2020-06-12 07:51:01 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2020-06-12 07:51:01 +0200 |
commit | d8b893bece3dfa2e421a7d92399fa913839c9220 (patch) | |
tree | a656ee768566572594d16258a95d1ddec8ea37ac /testsuite/synth/issue1366/issue_psl.vhdl | |
parent | db9c1fd3700995155b2d8a32d929b3d0dc9689e2 (diff) | |
download | ghdl-d8b893bece3dfa2e421a7d92399fa913839c9220.tar.gz ghdl-d8b893bece3dfa2e421a7d92399fa913839c9220.tar.bz2 ghdl-d8b893bece3dfa2e421a7d92399fa913839c9220.zip |
testsuite/synth: add test for #1366
Diffstat (limited to 'testsuite/synth/issue1366/issue_psl.vhdl')
-rw-r--r-- | testsuite/synth/issue1366/issue_psl.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/issue1366/issue_psl.vhdl b/testsuite/synth/issue1366/issue_psl.vhdl new file mode 100644 index 000000000..99ce6fbbf --- /dev/null +++ b/testsuite/synth/issue1366/issue_psl.vhdl @@ -0,0 +1,30 @@ +vunit issue_vunit (issue(psl)) { + + -- VHDL declaration seem to be working + signal a_delayed : std_logic := '0'; + + -- Other VHDL code not + -- results in parser errors + -- during synthesis + process is + begin + wait until rising_edge(clk); + a_delayed <= a; + end process; + + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion holds + CHECK_a : assert always (a -> b); + + -- You can't do anything with the declared signal + -- Can be synthesized with GHDL, however + -- results in error in ghdl-yosys-plugin: + -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:172 + assert always a_delayed = prev(a); + +} + + |