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authorTristan Gingold <tgingold@free.fr>2020-05-18 08:06:59 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-18 08:06:59 +0200
commit69bc02921c960dd3f15bf5ab3a589ebedb572197 (patch)
tree04f7e251e8efc6d85defc17de865b05bb52a9f35 /testsuite/synth/issue1319/repro2.vhdl
parent4291773d1d3e72f0beacce81b680d58634e9aaf0 (diff)
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testsuite/synth: add a test for #1319
Diffstat (limited to 'testsuite/synth/issue1319/repro2.vhdl')
-rw-r--r--testsuite/synth/issue1319/repro2.vhdl30
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diff --git a/testsuite/synth/issue1319/repro2.vhdl b/testsuite/synth/issue1319/repro2.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity repro2 is
+ port (
+ i : in std_ulogic_vector(1 downto 0);
+ o : out std_ulogic_vector (3 downto 0)
+ );
+end entity repro2;
+
+architecture behav of repro2 is
+ function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is
+ variable res : std_ulogic_vector (3 downto 0);
+ begin
+ case v is
+ when "01" =>
+ res := "1111";
+ when others =>
+ res := "0000";
+ return "0000";
+ end case;
+ return res;
+ end;
+
+begin
+ o <= func (i);
+end architecture behav;