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author | Tristan Gingold <tgingold@free.fr> | 2020-05-18 08:06:59 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-18 08:06:59 +0200 |
commit | 69bc02921c960dd3f15bf5ab3a589ebedb572197 (patch) | |
tree | 04f7e251e8efc6d85defc17de865b05bb52a9f35 /testsuite/synth/issue1319/repro2.vhdl | |
parent | 4291773d1d3e72f0beacce81b680d58634e9aaf0 (diff) | |
download | ghdl-69bc02921c960dd3f15bf5ab3a589ebedb572197.tar.gz ghdl-69bc02921c960dd3f15bf5ab3a589ebedb572197.tar.bz2 ghdl-69bc02921c960dd3f15bf5ab3a589ebedb572197.zip |
testsuite/synth: add a test for #1319
Diffstat (limited to 'testsuite/synth/issue1319/repro2.vhdl')
-rw-r--r-- | testsuite/synth/issue1319/repro2.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/issue1319/repro2.vhdl b/testsuite/synth/issue1319/repro2.vhdl new file mode 100644 index 000000000..7872e1163 --- /dev/null +++ b/testsuite/synth/issue1319/repro2.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity repro2 is + port ( + i : in std_ulogic_vector(1 downto 0); + o : out std_ulogic_vector (3 downto 0) + ); +end entity repro2; + +architecture behav of repro2 is + function func (v : std_ulogic_vector (1 downto 0)) return std_ulogic_vector is + variable res : std_ulogic_vector (3 downto 0); + begin + case v is + when "01" => + res := "1111"; + when others => + res := "0000"; + return "0000"; + end case; + return res; + end; + +begin + o <= func (i); +end architecture behav; |