testsuite/synth: add a test for #1318

4 files changed, 77 insertions, 0 deletions

diff --git a/testsuite/synth/issue1318/ram1.v b/testsuite/synth/issue1318/ram1.v
new file mode 100644
index 000000000..a5939c0e2
--- /dev/null
+++ b/testsuite/synth/issue1318/ram1.v
@@ -0,0 +1,10 @@
+(* RAM_STYLE="BLOCK" *)
+reg [7:0] lineMem [0:31];
+    
+reg [15:0]     column_data = 0;
+reg   [ADDR_BITS - 1:0]   line_mem_read_address  = 0;
+
+always @(posedge clk) begin 
+       column_data[7:0]     <= lineMem[line_mem_read_address];
+       column_data[15:8]   <= data_in;
+end
diff --git a/testsuite/synth/issue1318/ram2.v b/testsuite/synth/issue1318/ram2.v
new file mode 100644
index 000000000..c8f99f80a
--- /dev/null
+++ b/testsuite/synth/issue1318/ram2.v
@@ -0,0 +1,15 @@
+`default_nettype none
+module memory #(parameter W=8, D=64)
+   (input wire clk, wr_en,
+    input wire [W-1:0]  wr_addr, rd_addr,
+    input wire [D-1:0]  din,
+    output reg [D-1:0]  dout);
+
+   (*ram_style = "block"*)
+   reg [D-1:0]          mem [(1<<W)-1:0];
+
+   always @(posedge clk) begin
+      if(wr_en) mem[wr_addr] <= din;
+      dout <= mem[rd_addr];
+   end
+endmodule // memory
diff --git a/testsuite/synth/issue1318/ram_blk.vhdl b/testsuite/synth/issue1318/ram_blk.vhdl
new file mode 100644
index 000000000..85675d38a
--- /dev/null
+++ b/testsuite/synth/issue1318/ram_blk.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram_blk is
+    generic (
+      AWIDTH : integer := 8;
+      DWIDTH : integer := 64
+      );
+
+    port (
+	clk     : in  std_logic;
+	rd_addr : in  std_logic_vector(AWIDTH - 1 downto 0);
+	rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
+	wr_en   : in  std_logic;
+	wr_addr : in  std_logic_vector(AWIDTH - 1 downto 0);
+	wr_data : in  std_logic_vector(DWIDTH - 1 downto 0)
+	);
+
+end ram_blk;
+
+architecture rtl of ram_blk is
+  type ram_type is
+    array (0 to 2**AWIDTH - 1) of std_logic_vector(DWIDTH - 1 downto 0);
+
+  signal ram : ram_type;
+  attribute ram_style : string;
+  attribute ram_style of ram : signal is "block";
+  attribute ram_decomp : string;
+  attribute ram_decomp of ram : signal is "power";
+begin
+    process(clk)
+    begin
+	if rising_edge(clk) then
+	    if wr_en = '1' then
+              ram(to_integer(unsigned(wr_addr))) <= wr_data;
+	    end if;
+            rd_data <= ram(to_integer(unsigned(rd_addr)));
+	end if;
+    end process;
+end;
diff --git a/testsuite/synth/issue1318/testsuite.sh b/testsuite/synth/issue1318/testsuite.sh
new file mode 100755
index 000000000..c94e1ca90
--- /dev/null
+++ b/testsuite/synth/issue1318/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze ram_blk
+
+grep ram_style syn_ram_blk.vhdl
+
+clean
+
+echo "Test successful"