testsuite/synth: add a test for #1307

author: Tristan Gingold <tgingold@free.fr> 2020-05-16 07:29:47 +0200
committer: Tristan Gingold <tgingold@free.fr> 2020-05-16 07:29:47 +0200
commit: b9fc9fbf389a24201d05d649daeac782c864404e (patch)
tree: f5e16c669228196f8db8df9269dde6d5c02dc242 /testsuite/synth/issue1307
parent: 96b538b0241921d355382b8403f23d79927dfcae (diff)
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6 files changed, 1168 insertions, 0 deletions
diff --git a/testsuite/synth/issue1307/edge_enhance.vhd b/testsuite/synth/issue1307/edge_enhance.vhd
new file mode 100644
index 000000000..34c00b460
--- /dev/null
+++ b/testsuite/synth/issue1307/edge_enhance.vhd
@@ -0,0 +1,102 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity edge_enhance is
+    Port (  clk            : in STD_LOGIC;
+            enable_feature : in std_logic;
+            -------------------------------
+            -- VGA data recovered from HDMI
+            -------------------------------
+            in_blank  : in std_logic;
+            in_hsync  : in std_logic;
+            in_vsync  : in std_logic;
+            in_red    : in std_logic_vector(7 downto 0);
+            in_green  : in std_logic_vector(7 downto 0);
+            in_blue   : in std_logic_vector(7 downto 0);
+            -----------------------------------
+            -- VGA data to be converted to HDMI
+            -----------------------------------
+            out_blank : out std_logic;
+            out_hsync : out std_logic;
+            out_vsync : out std_logic;
+            out_red   : out std_logic_vector(7 downto 0);
+            out_green : out std_logic_vector(7 downto 0);
+            out_blue  : out std_logic_vector(7 downto 0));
+end edge_enhance;
+
+architecture Behavioral of edge_enhance is
+    component line_delay is
+    Port ( clk : in STD_LOGIC;
+           -------------------------------
+           -- VGA data recovered from HDMI
+           -------------------------------
+           in_blank  : in std_logic;
+           in_hsync  : in std_logic;
+           in_vsync  : in std_logic;
+           in_red    : in std_logic_vector(7 downto 0);
+           in_green  : in std_logic_vector(7 downto 0);
+           in_blue   : in std_logic_vector(7 downto 0);
+     
+           -----------------------------------
+           -- VGA data to be converted to HDMI
+           -----------------------------------
+           out_blank : out std_logic;
+           out_hsync : out std_logic;
+           out_vsync : out std_logic;
+           out_red   : out std_logic_vector(7 downto 0);
+           out_green : out std_logic_vector(7 downto 0);
+           out_blue  : out std_logic_vector(7 downto 0));
+    end component;
+    type a_bits is array(0 to 8) of std_logic;
+    type a_component is array(0 to 8) of std_logic_vector(7 downto 0);
+    signal blanks : a_bits;
+    signal hsyncs : a_bits;
+    signal vsyncs : a_bits;
+    signal reds   : a_component;
+    signal greens : a_component;
+    signal blues  : a_component;
+
+    signal sobel_1_blue   : unsigned(12 downto 0) := (others => '0');
+    signal sobel_1_blue_x  : unsigned(11 downto 0) := (others => '0');
+    signal sobel_1_blue_y  : unsigned(11 downto 0) := (others => '0');
+
+    signal sobel_3_blue   : unsigned(12 downto 0) := (others => '0');
+    signal sobel_2_blue_x  : unsigned(11 downto 0) := (others => '0');
+    signal sobel_2_blue_y  : unsigned(11 downto 0) := (others => '0');
+
+    signal sobel_1_green_left   : unsigned(11 downto 0) := (others => '0');
+    signal sobel_1_green_right  : unsigned(11 downto 0) := (others => '0');
+    signal sobel_1_blue_left    : unsigned(11 downto 0) := (others => '0');
+    signal sobel_1_blue_right   : unsigned(11 downto 0) := (others => '0');
+
+    signal test : std_logic_vector(7 downto 0) := (others => '0');
+    signal test2 : std_logic_vector(7 downto 0) := (others => '0');
+begin
+
+i_line_delay_2: line_delay  Port map ( 
+        clk       => clk,
+        in_blank  => blanks(3),
+        in_hsync  => hsyncs(3),
+        in_vsync  => vsyncs(3),
+        in_red    => reds(3),
+        in_green  => greens(3),
+        in_blue   => blues(3),
+
+        out_blank => blanks(6), 
+        out_hsync => hsyncs(6),
+        out_vsync => vsyncs(6), 
+        out_red   => reds(6),
+        out_green => test2, 
+        out_blue  => test  
+    );
+
+process(clk)
+    begin
+        if rising_edge(clk) then
+		out_green <= test2;
+		out_blue <= test;
+        end if;
+    end process;
+
+end Behavioral;
diff --git a/testsuite/synth/issue1307/hdmi_design.vhd b/testsuite/synth/issue1307/hdmi_design.vhd
new file mode 100644
index 000000000..5427a7c40
--- /dev/null
+++ b/testsuite/synth/issue1307/hdmi_design.vhd
@@ -0,0 +1,211 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity hdmi_design is
+    Port ( 
+        clk100    : in STD_LOGIC;
+        -- Control signals
+        led           : out   std_logic_vector(7 downto 0) :=(others => '0');
+        sw            : in    std_logic_vector(7 downto 0) :=(others => '0');
+        debug_pmod    : out   std_logic_vector(7 downto 0) :=(others => '0');
+
+        --HDMI input signals
+        hdmi_rx_cec   : inout std_logic;
+        hdmi_rx_hpa   : out   std_logic;
+        hdmi_rx_scl   : in    std_logic;
+        hdmi_rx_sda   : inout std_logic;
+        hdmi_rx_txen  : out   std_logic;
+        hdmi_rx_clk_n : in    std_logic;
+        hdmi_rx_clk_p : in    std_logic;
+        hdmi_rx_n     : in    std_logic_vector(2 downto 0);
+        hdmi_rx_p     : in    std_logic_vector(2 downto 0);
+
+        --- HDMI out
+        hdmi_tx_cec   : inout std_logic;
+        hdmi_tx_clk_n : out   std_logic;
+        hdmi_tx_clk_p : out   std_logic;
+        hdmi_tx_hpd   : in    std_logic;
+        hdmi_tx_rscl  : inout std_logic;
+        hdmi_tx_rsda  : inout std_logic;
+        hdmi_tx_p     : out   std_logic_vector(2 downto 0);
+        hdmi_tx_n     : out   std_logic_vector(2 downto 0);
+        -- For dumping symbols
+        rs232_tx     : out std_logic      
+    );
+end hdmi_design;
+
+architecture Behavioral of hdmi_design is
+    component hdmi_io is
+    Port ( 
+        clk100    : in STD_LOGIC;
+        -------------------------------
+        -- Control signals
+        -------------------------------
+        clock_locked  : out std_logic;
+        data_synced   : out std_logic;
+        debug         : out std_logic_vector(7 downto 0);        
+        -------------------------------
+        --HDMI input signals
+        -------------------------------
+        hdmi_rx_cec   : inout std_logic;
+        hdmi_rx_hpa   : out   std_logic;
+        hdmi_rx_scl   : in    std_logic;
+        hdmi_rx_sda   : inout std_logic;
+        hdmi_rx_txen  : out   std_logic;
+        hdmi_rx_clk_n : in    std_logic;
+        hdmi_rx_clk_p : in    std_logic;
+        hdmi_rx_n     : in    std_logic_vector(2 downto 0);
+        hdmi_rx_p     : in    std_logic_vector(2 downto 0);
+
+        -------------
+        -- HDMI out
+        -------------
+        hdmi_tx_cec   : inout std_logic;
+        hdmi_tx_clk_n : out   std_logic;
+        hdmi_tx_clk_p : out   std_logic;
+        hdmi_tx_hpd   : in    std_logic;
+        hdmi_tx_rscl  : inout std_logic;
+        hdmi_tx_rsda  : inout std_logic;
+        hdmi_tx_p     : out   std_logic_vector(2 downto 0);
+        hdmi_tx_n     : out   std_logic_vector(2 downto 0);
+
+        pixel_clk     : out std_logic;
+        -------------------------------
+        -- VGA data recovered from HDMI
+        -------------------------------
+        in_hdmi_detected : out std_logic;
+        in_blank        : out std_logic;
+        in_hsync        : out std_logic;
+        in_vsync        : out std_logic;
+        in_red          : out std_logic_vector(7 downto 0);
+        in_green        : out std_logic_vector(7 downto 0);
+        in_blue         : out std_logic_vector(7 downto 0);
+        is_interlaced   : out std_logic;
+        is_second_field : out std_logic;
+            
+        -------------------------------------
+        -- Audio Levels
+        -------------------------------------
+        audio_channel : out std_logic_vector(2 downto 0);
+        audio_de      : out std_logic;
+        audio_sample  : out std_logic_vector(23 downto 0);
+        
+        -----------------------------------
+        -- VGA data to be converted to HDMI
+        -----------------------------------
+        out_blank     : in  std_logic;
+        out_hsync     : in  std_logic;
+        out_vsync     : in  std_logic;
+        out_red       : in  std_logic_vector(7 downto 0);
+        out_green     : in  std_logic_vector(7 downto 0);
+        out_blue      : in  std_logic_vector(7 downto 0);
+        -----------------------------------
+        -- For symbol dump or retransmit
+        -----------------------------------
+        symbol_sync  : out std_logic; -- indicates a fixed reference point in the frame.
+        symbol_ch0   : out std_logic_vector(9 downto 0);
+        symbol_ch1   : out std_logic_vector(9 downto 0);
+        symbol_ch2   : out std_logic_vector(9 downto 0)
+    );
+    end component;
+    signal symbol_sync  : std_logic;
+    signal symbol_ch0   : std_logic_vector(9 downto 0);
+    signal symbol_ch1   : std_logic_vector(9 downto 0);
+    signal symbol_ch2   : std_logic_vector(9 downto 0);
+    
+    component pixel_processing is
+        Port ( clk : in STD_LOGIC;
+            switches  : in std_logic_vector(7 downto 0);
+            ------------------
+            -- Incoming pixels
+            ------------------
+            in_blank  : in std_logic;
+            in_hsync  : in std_logic;
+            in_vsync  : in std_logic;
+            in_red    : in std_logic_vector(7 downto 0);
+            in_green  : in std_logic_vector(7 downto 0);
+            in_blue   : in std_logic_vector(7 downto 0);
+            is_interlaced   : in  std_logic;
+            is_second_field : in  std_logic;
+        
+            -------------------
+            -- Processed pixels
+            -------------------
+            out_blank : out std_logic;
+            out_hsync : out std_logic;
+            out_vsync : out std_logic;
+            out_red   : out std_logic_vector(7 downto 0);
+            out_green : out std_logic_vector(7 downto 0);
+            out_blue  : out std_logic_vector(7 downto 0);
+                       
+            -------------------------------------
+            -- Audio samples for metering
+            -------------------------------------
+            audio_channel : in std_logic_vector(2 downto 0);
+            audio_de      : in std_logic;
+            audio_sample  : in std_logic_vector(23 downto 0)
+    );
+    end component;
+
+    component symbol_dump is
+        port ( 
+            clk          : in std_logic;
+            clk100       : in std_logic;
+            symbol_sync  : in std_logic; -- indicates a fixed reference point in the frame.
+            symbol_ch0   : in std_logic_vector(9 downto 0);
+            symbol_ch1   : in std_logic_vector(9 downto 0);
+            symbol_ch2   : in std_logic_vector(9 downto 0);
+            rs232_tx     : out std_logic);        
+    end component;
+
+    signal pixel_clk : std_logic;
+    signal in_blank  : std_logic;
+    signal in_hsync  : std_logic;
+    signal in_vsync  : std_logic;
+    signal in_red    : std_logic_vector(7 downto 0);
+    signal in_green  : std_logic_vector(7 downto 0);
+    signal in_blue   : std_logic_vector(7 downto 0);
+    signal is_interlaced   : std_logic;
+    signal is_second_field : std_logic;
+    signal out_blank : std_logic;
+    signal out_hsync : std_logic;
+    signal out_vsync : std_logic;
+    signal out_red   : std_logic_vector(7 downto 0);
+    signal out_green : std_logic_vector(7 downto 0);
+    signal out_blue  : std_logic_vector(7 downto 0);
+
+    signal audio_channel : std_logic_vector(2 downto 0);
+    signal audio_de      : std_logic;
+    signal audio_sample  : std_logic_vector(23 downto 0);
+
+    signal debug : std_logic_vector(7 downto 0);
+begin
+i_processing: pixel_processing Port map ( 
+        clk => pixel_clk,
+        switches => sw,
+        ------------------
+        -- Incoming pixels
+        ------------------
+        in_blank        => in_blank,
+        in_hsync        => in_hsync,
+        in_vsync        => in_vsync,
+        in_red          => in_red,
+        in_green        => in_green,
+        in_blue         => in_blue,    
+        is_interlaced   => is_interlaced,
+        is_second_field => is_second_field,
+        audio_channel   => audio_channel,
+        audio_de        => audio_de,
+        audio_sample    => audio_sample,
+        -------------------
+        -- Processed pixels
+        -------------------
+        out_blank => out_blank,
+        out_hsync => out_hsync,
+        out_vsync => out_vsync,
+        out_red   => out_red,
+        out_green => out_green,
+        out_blue  => out_blue
+    );
+
+end Behavioral;
diff --git a/testsuite/synth/issue1307/line_delay.vhd b/testsuite/synth/issue1307/line_delay.vhd
new file mode 100644
index 000000000..cfbaca7cc
--- /dev/null
+++ b/testsuite/synth/issue1307/line_delay.vhd
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity line_delay is
+    Port ( clk : in STD_LOGIC;
+           -------------------------------
+           -- VGA data recovered from HDMI
+           -------------------------------
+           in_blank  : in std_logic;
+           in_hsync  : in std_logic;
+           in_vsync  : in std_logic;
+           in_red    : in std_logic_vector(7 downto 0);
+           in_green  : in std_logic_vector(7 downto 0);
+           in_blue   : in std_logic_vector(7 downto 0);
+     
+           -----------------------------------
+           -- VGA data to be converted to HDMI
+           -----------------------------------
+           out_blank : out std_logic;
+           out_hsync : out std_logic;
+           out_vsync : out std_logic;
+           out_red   : out std_logic_vector(7 downto 0);
+           out_green : out std_logic_vector(7 downto 0);
+           out_blue  : out std_logic_vector(7 downto 0));
+end line_delay;
+
+architecture Behavioral of line_delay is
+    type mem_block is array (0 to 511) of std_logic_vector(26 downto 0);
+    signal mem_4 : mem_block := (others => (others => '0'));
+    signal wr_addr    : unsigned(8 downto 0) := (others =>'1');
+    signal mid_3      : std_logic_vector(26 downto 0) := (others =>'0');
+begin
+
+process(clk)
+    variable mem_4_out : std_logic_vector(26 downto 0);
+    begin
+        if rising_edge(clk) then
+            mem_4_out := mem_4(to_integer(wr_addr));
+            out_green <= mem_4_out(18 downto 11);
+            out_blue  <= mem_4_out(10 downto  3);
+            mem_4(to_integer(wr_addr)) <= mid_3;
+        end if;
+    end process;
+
+end Behavioral;
diff --git a/testsuite/synth/issue1307/pixel_processing.vhd b/testsuite/synth/issue1307/pixel_processing.vhd
new file mode 100644
index 000000000..895030ddb
--- /dev/null
+++ b/testsuite/synth/issue1307/pixel_processing.vhd
@@ -0,0 +1,130 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity pixel_processing is
+    Port ( clk : in STD_LOGIC;
+            -------------------------------
+            -- VGA data recovered from HDMI
+            -------------------------------
+            in_blank  : in std_logic;
+            in_hsync  : in std_logic;
+            in_vsync  : in std_logic;
+            in_red    : in std_logic_vector(7 downto 0);
+            in_green  : in std_logic_vector(7 downto 0);
+            in_blue   : in std_logic_vector(7 downto 0);
+            is_interlaced   : in std_logic;
+            is_second_field : in std_logic;
+            -----------------------------------
+            -- VGA data to be converted to HDMI
+            -----------------------------------
+            out_blank : out std_logic;
+            out_hsync : out std_logic;
+            out_vsync : out std_logic;
+            out_red   : out std_logic_vector(7 downto 0);
+            out_green : out std_logic_vector(7 downto 0);
+            out_blue  : out std_logic_vector(7 downto 0);
+            ------------------------------------
+            -- Audio only comes in..
+            ------------------------------------
+            audio_channel : in std_logic_vector(2 downto 0);
+            audio_de      : in std_logic;
+            audio_sample  : in std_logic_vector(23 downto 0);
+      
+            ----------------------------------
+            -- Controls
+            ----------------------------------   
+            switches : in std_logic_vector(7 downto 0)
+    );
+end pixel_processing;
+
+architecture Behavioral of pixel_processing is
+    component edge_enhance is
+    Port ( clk : in STD_LOGIC;
+           enable_feature   : in std_logic;
+           -------------------------------
+           -- VGA data recovered from HDMI
+           -------------------------------
+           in_blank  : in std_logic;
+           in_hsync  : in std_logic;
+           in_vsync  : in std_logic;
+           in_red    : in std_logic_vector(7 downto 0);
+           in_green  : in std_logic_vector(7 downto 0);
+           in_blue   : in std_logic_vector(7 downto 0);
+            
+           -----------------------------------
+           -- VGA data to be converted to HDMI
+           -----------------------------------
+           out_blank : out std_logic;
+           out_hsync : out std_logic;
+           out_vsync : out std_logic;
+           out_red   : out std_logic_vector(7 downto 0);
+           out_green : out std_logic_vector(7 downto 0);
+           out_blue  : out std_logic_vector(7 downto 0)
+    );
+    end component;
+
+    component guidelines is
+    Port ( clk : in STD_LOGIC;
+           enable_feature   : in std_logic;
+           -------------------------------
+           -- VGA data recovered from HDMI
+           -------------------------------
+           in_blank  : in std_logic;
+           in_hsync  : in std_logic;
+           in_vsync  : in std_logic;
+           in_red    : in std_logic_vector(7 downto 0);
+           in_green  : in std_logic_vector(7 downto 0);
+           in_blue   : in std_logic_vector(7 downto 0);
+           is_interlaced   : in std_logic;
+           is_second_field : in std_logic;
+            
+           -----------------------------------
+           -- VGA data to be converted to HDMI
+           -----------------------------------
+           out_blank : out std_logic;
+           out_hsync : out std_logic;
+           out_vsync : out std_logic;
+           out_red   : out std_logic_vector(7 downto 0);
+           out_green : out std_logic_vector(7 downto 0);
+           out_blue  : out std_logic_vector(7 downto 0)
+    );
+    end component;
+    
+    signal b_blank : std_logic;
+    signal b_hsync : std_logic;
+    signal b_vsync : std_logic;
+    signal b_red   : std_logic_vector(7 downto 0);
+    signal b_green : std_logic_vector(7 downto 0);
+    signal b_blue  : std_logic_vector(7 downto 0);
+
+    signal c_blank : std_logic;
+    signal c_hsync : std_logic;
+    signal c_vsync : std_logic;
+    signal c_red   : std_logic_vector(7 downto 0);
+    signal c_green : std_logic_vector(7 downto 0);
+    signal c_blue  : std_logic_vector(7 downto 0);
+
+begin
+
+i_edge_enhance: edge_enhance Port map ( 
+        clk       => clk,
+        
+        enable_feature => switches(0),
+
+        in_blank  => in_blank,
+        in_hsync  => in_hsync,
+        in_vsync  => in_vsync,
+        in_red    => in_red,
+        in_green  => in_green,
+        in_blue   => in_blue,
+       
+        out_blank => b_blank,
+        out_hsync => b_hsync,
+        out_vsync => b_vsync,
+        out_red   => b_red,
+        out_green => b_green,
+        out_blue  => b_blue
+    );
+
+ end Behavioral;
diff --git a/testsuite/synth/issue1307/test.v b/testsuite/synth/issue1307/test.v
new file mode 100644
index 000000000..35cae210b
--- /dev/null
+++ b/testsuite/synth/issue1307/test.v
@@ -0,0 +1,672 @@
+/* Generated by Yosys 0.9+2406 (git sha1 aafaeb66, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
+
+module edge_enhance(clk, enable_feature, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
+  reg [7:0] _0_;
+  reg [7:0] _1_;
+  input clk;
+  input enable_feature;
+  wire \i_line_delay_2%126 ;
+  wire \i_line_delay_2%127 ;
+  wire \i_line_delay_2%128 ;
+  wire [7:0] \i_line_delay_2%129 ;
+  wire [7:0] \i_line_delay_2%130 ;
+  wire [7:0] \i_line_delay_2%131 ;
+  input in_blank;
+  input [7:0] in_blue;
+  input [7:0] in_green;
+  input in_hsync;
+  input [7:0] in_red;
+  input in_vsync;
+  output out_blank;
+  output [7:0] out_blue;
+  output [7:0] out_green;
+  output out_hsync;
+  output [7:0] out_red;
+  output out_vsync;
+  always @(posedge clk)
+      _0_ <= \i_line_delay_2%130 ;
+  always @(posedge clk)
+      _1_ <= \i_line_delay_2%131 ;
+  line_delay i_line_delay_2 (
+    .clk(clk),
+    .in_blank(1'hz),
+    .in_blue(8'hxx),
+    .in_green(8'hxx),
+    .in_hsync(1'hz),
+    .in_red(8'hzz),
+    .in_vsync(1'hz),
+    .out_blank(\i_line_delay_2%126 ),
+    .out_blue(\i_line_delay_2%131 ),
+    .out_green(\i_line_delay_2%130 ),
+    .out_hsync(\i_line_delay_2%127 ),
+    .out_red(\i_line_delay_2%129 ),
+    .out_vsync(\i_line_delay_2%128 )
+  );
+  assign out_blank = 1'hz;
+  assign out_hsync = 1'hz;
+  assign out_vsync = 1'hz;
+  assign out_red = 8'hzz;
+  assign out_green = _0_;
+  assign out_blue = _1_;
+endmodule
+
+module hdmi_design(clk100, sw, hdmi_rx_scl, hdmi_rx_clk_n, hdmi_rx_clk_p, hdmi_rx_n, hdmi_rx_p, hdmi_tx_hpd, led, debug_pmod, hdmi_rx_cec, hdmi_rx_hpa, hdmi_rx_sda, hdmi_rx_txen, hdmi_tx_cec, hdmi_tx_clk_n, hdmi_tx_clk_p, hdmi_tx_rscl, hdmi_tx_rsda, hdmi_tx_p, hdmi_tx_n, rs232_tx);
+  input clk100;
+  output [7:0] debug_pmod;
+  inout hdmi_rx_cec;
+  input hdmi_rx_clk_n;
+  input hdmi_rx_clk_p;
+  output hdmi_rx_hpa;
+  input [2:0] hdmi_rx_n;
+  input [2:0] hdmi_rx_p;
+  input hdmi_rx_scl;
+  inout hdmi_rx_sda;
+  output hdmi_rx_txen;
+  inout hdmi_tx_cec;
+  output hdmi_tx_clk_n;
+  output hdmi_tx_clk_p;
+  input hdmi_tx_hpd;
+  output [2:0] hdmi_tx_n;
+  output [2:0] hdmi_tx_p;
+  inout hdmi_tx_rscl;
+  inout hdmi_tx_rsda;
+  output [7:0] led;
+  output rs232_tx;
+  input [7:0] sw;
+  assign hdmi_rx_cec = 1'hz;
+  assign hdmi_rx_sda = 1'hz;
+  assign hdmi_tx_cec = 1'hz;
+  assign hdmi_tx_rscl = 1'hz;
+  assign hdmi_tx_rsda = 1'hz;
+  assign led = 8'hzz;
+  assign debug_pmod = 8'hzz;
+  assign hdmi_rx_hpa = 1'hz;
+  assign hdmi_rx_txen = 1'hz;
+  assign hdmi_tx_clk_n = 1'hz;
+  assign hdmi_tx_clk_p = 1'hz;
+  assign hdmi_tx_p = 3'hz;
+  assign hdmi_tx_n = 3'hz;
+  assign rs232_tx = 1'hz;
+endmodule
+
+module line_delay(clk, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
+  wire [8:0] _0_;
+  reg [7:0] _1_;
+  reg [7:0] _2_;
+  wire [13823:0] _3_;
+  wire [26:0] _4_;
+  wire [8:0] _5_;
+  input clk;
+  input in_blank;
+  input [7:0] in_blue;
+  input [7:0] in_green;
+  input in_hsync;
+  input [7:0] in_red;
+  input in_vsync;
+  output out_blank;
+  output [7:0] out_blue;
+  output [7:0] out_green;
+  output out_hsync;
+  output [7:0] out_red;
+  output out_vsync;
+  reg [26:0] \$mem$\208  [511:0];
+  assign _5_ = 9'h1ff - 9'h1ff;
+  assign _0_ = 9'h1ff - 9'h1ff;
+  always @(posedge clk)
+      _1_ <= _4_[18:11];
+  always @(posedge clk)
+      _2_ <= _4_[10:3];
+  reg [26:0] \208  [511:0];
+  initial begin
+    \208 [0] = 27'h0000000;
+    \208 [1] = 27'h0000000;
+    \208 [2] = 27'h0000000;
+    \208 [3] = 27'h0000000;
+    \208 [4] = 27'h0000000;
+    \208 [5] = 27'h0000000;
+    \208 [6] = 27'h0000000;
+    \208 [7] = 27'h0000000;
+    \208 [8] = 27'h0000000;
+    \208 [9] = 27'h0000000;
+    \208 [10] = 27'h0000000;
+    \208 [11] = 27'h0000000;
+    \208 [12] = 27'h0000000;
+    \208 [13] = 27'h0000000;
+    \208 [14] = 27'h0000000;
+    \208 [15] = 27'h0000000;
+    \208 [16] = 27'h0000000;
+    \208 [17] = 27'h0000000;
+    \208 [18] = 27'h0000000;
+    \208 [19] = 27'h0000000;
+    \208 [20] = 27'h0000000;
+    \208 [21] = 27'h0000000;
+    \208 [22] = 27'h0000000;
+    \208 [23] = 27'h0000000;
+    \208 [24] = 27'h0000000;
+    \208 [25] = 27'h0000000;
+    \208 [26] = 27'h0000000;
+    \208 [27] = 27'h0000000;
+    \208 [28] = 27'h0000000;
+    \208 [29] = 27'h0000000;
+    \208 [30] = 27'h0000000;
+    \208 [31] = 27'h0000000;
+    \208 [32] = 27'h0000000;
+    \208 [33] = 27'h0000000;
+    \208 [34] = 27'h0000000;
+    \208 [35] = 27'h0000000;
+    \208 [36] = 27'h0000000;
+    \208 [37] = 27'h0000000;
+    \208 [38] = 27'h0000000;
+    \208 [39] = 27'h0000000;
+    \208 [40] = 27'h0000000;
+    \208 [41] = 27'h0000000;
+    \208 [42] = 27'h0000000;
+    \208 [43] = 27'h0000000;
+    \208 [44] = 27'h0000000;
+    \208 [45] = 27'h0000000;
+    \208 [46] = 27'h0000000;
+    \208 [47] = 27'h0000000;
+    \208 [48] = 27'h0000000;
+    \208 [49] = 27'h0000000;
+    \208 [50] = 27'h0000000;
+    \208 [51] = 27'h0000000;
+    \208 [52] = 27'h0000000;
+    \208 [53] = 27'h0000000;
+    \208 [54] = 27'h0000000;
+    \208 [55] = 27'h0000000;
+    \208 [56] = 27'h0000000;
+    \208 [57] = 27'h0000000;
+    \208 [58] = 27'h0000000;
+    \208 [59] = 27'h0000000;
+    \208 [60] = 27'h0000000;
+    \208 [61] = 27'h0000000;
+    \208 [62] = 27'h0000000;
+    \208 [63] = 27'h0000000;
+    \208 [64] = 27'h0000000;
+    \208 [65] = 27'h0000000;
+    \208 [66] = 27'h0000000;
+    \208 [67] = 27'h0000000;
+    \208 [68] = 27'h0000000;
+    \208 [69] = 27'h0000000;
+    \208 [70] = 27'h0000000;
+    \208 [71] = 27'h0000000;
+    \208 [72] = 27'h0000000;
+    \208 [73] = 27'h0000000;
+    \208 [74] = 27'h0000000;
+    \208 [75] = 27'h0000000;
+    \208 [76] = 27'h0000000;
+    \208 [77] = 27'h0000000;
+    \208 [78] = 27'h0000000;
+    \208 [79] = 27'h0000000;
+    \208 [80] = 27'h0000000;
+    \208 [81] = 27'h0000000;
+    \208 [82] = 27'h0000000;
+    \208 [83] = 27'h0000000;
+    \208 [84] = 27'h0000000;
+    \208 [85] = 27'h0000000;
+    \208 [86] = 27'h0000000;
+    \208 [87] = 27'h0000000;
+    \208 [88] = 27'h0000000;
+    \208 [89] = 27'h0000000;
+    \208 [90] = 27'h0000000;
+    \208 [91] = 27'h0000000;
+    \208 [92] = 27'h0000000;
+    \208 [93] = 27'h0000000;
+    \208 [94] = 27'h0000000;
+    \208 [95] = 27'h0000000;
+    \208 [96] = 27'h0000000;
+    \208 [97] = 27'h0000000;
+    \208 [98] = 27'h0000000;
+    \208 [99] = 27'h0000000;
+    \208 [100] = 27'h0000000;
+    \208 [101] = 27'h0000000;
+    \208 [102] = 27'h0000000;
+    \208 [103] = 27'h0000000;
+    \208 [104] = 27'h0000000;
+    \208 [105] = 27'h0000000;
+    \208 [106] = 27'h0000000;
+    \208 [107] = 27'h0000000;
+    \208 [108] = 27'h0000000;
+    \208 [109] = 27'h0000000;
+    \208 [110] = 27'h0000000;
+    \208 [111] = 27'h0000000;
+    \208 [112] = 27'h0000000;
+    \208 [113] = 27'h0000000;
+    \208 [114] = 27'h0000000;
+    \208 [115] = 27'h0000000;
+    \208 [116] = 27'h0000000;
+    \208 [117] = 27'h0000000;
+    \208 [118] = 27'h0000000;
+    \208 [119] = 27'h0000000;
+    \208 [120] = 27'h0000000;
+    \208 [121] = 27'h0000000;
+    \208 [122] = 27'h0000000;
+    \208 [123] = 27'h0000000;
+    \208 [124] = 27'h0000000;
+    \208 [125] = 27'h0000000;
+    \208 [126] = 27'h0000000;
+    \208 [127] = 27'h0000000;
+    \208 [128] = 27'h0000000;
+    \208 [129] = 27'h0000000;
+    \208 [130] = 27'h0000000;
+    \208 [131] = 27'h0000000;
+    \208 [132] = 27'h0000000;
+    \208 [133] = 27'h0000000;
+    \208 [134] = 27'h0000000;
+    \208 [135] = 27'h0000000;
+    \208 [136] = 27'h0000000;
+    \208 [137] = 27'h0000000;
+    \208 [138] = 27'h0000000;
+    \208 [139] = 27'h0000000;
+    \208 [140] = 27'h0000000;
+    \208 [141] = 27'h0000000;
+    \208 [142] = 27'h0000000;
+    \208 [143] = 27'h0000000;
+    \208 [144] = 27'h0000000;
+    \208 [145] = 27'h0000000;
+    \208 [146] = 27'h0000000;
+    \208 [147] = 27'h0000000;
+    \208 [148] = 27'h0000000;
+    \208 [149] = 27'h0000000;
+    \208 [150] = 27'h0000000;
+    \208 [151] = 27'h0000000;
+    \208 [152] = 27'h0000000;
+    \208 [153] = 27'h0000000;
+    \208 [154] = 27'h0000000;
+    \208 [155] = 27'h0000000;
+    \208 [156] = 27'h0000000;
+    \208 [157] = 27'h0000000;
+    \208 [158] = 27'h0000000;
+    \208 [159] = 27'h0000000;
+    \208 [160] = 27'h0000000;
+    \208 [161] = 27'h0000000;
+    \208 [162] = 27'h0000000;
+    \208 [163] = 27'h0000000;
+    \208 [164] = 27'h0000000;
+    \208 [165] = 27'h0000000;
+    \208 [166] = 27'h0000000;
+    \208 [167] = 27'h0000000;
+    \208 [168] = 27'h0000000;
+    \208 [169] = 27'h0000000;
+    \208 [170] = 27'h0000000;
+    \208 [171] = 27'h0000000;
+    \208 [172] = 27'h0000000;
+    \208 [173] = 27'h0000000;
+    \208 [174] = 27'h0000000;
+    \208 [175] = 27'h0000000;
+    \208 [176] = 27'h0000000;
+    \208 [177] = 27'h0000000;
+    \208 [178] = 27'h0000000;
+    \208 [179] = 27'h0000000;
+    \208 [180] = 27'h0000000;
+    \208 [181] = 27'h0000000;
+    \208 [182] = 27'h0000000;
+    \208 [183] = 27'h0000000;
+    \208 [184] = 27'h0000000;
+    \208 [185] = 27'h0000000;
+    \208 [186] = 27'h0000000;
+    \208 [187] = 27'h0000000;
+    \208 [188] = 27'h0000000;
+    \208 [189] = 27'h0000000;
+    \208 [190] = 27'h0000000;
+    \208 [191] = 27'h0000000;
+    \208 [192] = 27'h0000000;
+    \208 [193] = 27'h0000000;
+    \208 [194] = 27'h0000000;
+    \208 [195] = 27'h0000000;
+    \208 [196] = 27'h0000000;
+    \208 [197] = 27'h0000000;
+    \208 [198] = 27'h0000000;
+    \208 [199] = 27'h0000000;
+    \208 [200] = 27'h0000000;
+    \208 [201] = 27'h0000000;
+    \208 [202] = 27'h0000000;
+    \208 [203] = 27'h0000000;
+    \208 [204] = 27'h0000000;
+    \208 [205] = 27'h0000000;
+    \208 [206] = 27'h0000000;
+    \208 [207] = 27'h0000000;
+    \208 [208] = 27'h0000000;
+    \208 [209] = 27'h0000000;
+    \208 [210] = 27'h0000000;
+    \208 [211] = 27'h0000000;
+    \208 [212] = 27'h0000000;
+    \208 [213] = 27'h0000000;
+    \208 [214] = 27'h0000000;
+    \208 [215] = 27'h0000000;
+    \208 [216] = 27'h0000000;
+    \208 [217] = 27'h0000000;
+    \208 [218] = 27'h0000000;
+    \208 [219] = 27'h0000000;
+    \208 [220] = 27'h0000000;
+    \208 [221] = 27'h0000000;
+    \208 [222] = 27'h0000000;
+    \208 [223] = 27'h0000000;
+    \208 [224] = 27'h0000000;
+    \208 [225] = 27'h0000000;
+    \208 [226] = 27'h0000000;
+    \208 [227] = 27'h0000000;
+    \208 [228] = 27'h0000000;
+    \208 [229] = 27'h0000000;
+    \208 [230] = 27'h0000000;
+    \208 [231] = 27'h0000000;
+    \208 [232] = 27'h0000000;
+    \208 [233] = 27'h0000000;
+    \208 [234] = 27'h0000000;
+    \208 [235] = 27'h0000000;
+    \208 [236] = 27'h0000000;
+    \208 [237] = 27'h0000000;
+    \208 [238] = 27'h0000000;
+    \208 [239] = 27'h0000000;
+    \208 [240] = 27'h0000000;
+    \208 [241] = 27'h0000000;
+    \208 [242] = 27'h0000000;
+    \208 [243] = 27'h0000000;
+    \208 [244] = 27'h0000000;
+    \208 [245] = 27'h0000000;
+    \208 [246] = 27'h0000000;
+    \208 [247] = 27'h0000000;
+    \208 [248] = 27'h0000000;
+    \208 [249] = 27'h0000000;
+    \208 [250] = 27'h0000000;
+    \208 [251] = 27'h0000000;
+    \208 [252] = 27'h0000000;
+    \208 [253] = 27'h0000000;
+    \208 [254] = 27'h0000000;
+    \208 [255] = 27'h0000000;
+    \208 [256] = 27'h0000000;
+    \208 [257] = 27'h0000000;
+    \208 [258] = 27'h0000000;
+    \208 [259] = 27'h0000000;
+    \208 [260] = 27'h0000000;
+    \208 [261] = 27'h0000000;
+    \208 [262] = 27'h0000000;
+    \208 [263] = 27'h0000000;
+    \208 [264] = 27'h0000000;
+    \208 [265] = 27'h0000000;
+    \208 [266] = 27'h0000000;
+    \208 [267] = 27'h0000000;
+    \208 [268] = 27'h0000000;
+    \208 [269] = 27'h0000000;
+    \208 [270] = 27'h0000000;
+    \208 [271] = 27'h0000000;
+    \208 [272] = 27'h0000000;
+    \208 [273] = 27'h0000000;
+    \208 [274] = 27'h0000000;
+    \208 [275] = 27'h0000000;
+    \208 [276] = 27'h0000000;
+    \208 [277] = 27'h0000000;
+    \208 [278] = 27'h0000000;
+    \208 [279] = 27'h0000000;
+    \208 [280] = 27'h0000000;
+    \208 [281] = 27'h0000000;
+    \208 [282] = 27'h0000000;
+    \208 [283] = 27'h0000000;
+    \208 [284] = 27'h0000000;
+    \208 [285] = 27'h0000000;
+    \208 [286] = 27'h0000000;
+    \208 [287] = 27'h0000000;
+    \208 [288] = 27'h0000000;
+    \208 [289] = 27'h0000000;
+    \208 [290] = 27'h0000000;
+    \208 [291] = 27'h0000000;
+    \208 [292] = 27'h0000000;
+    \208 [293] = 27'h0000000;
+    \208 [294] = 27'h0000000;
+    \208 [295] = 27'h0000000;
+    \208 [296] = 27'h0000000;
+    \208 [297] = 27'h0000000;
+    \208 [298] = 27'h0000000;
+    \208 [299] = 27'h0000000;
+    \208 [300] = 27'h0000000;
+    \208 [301] = 27'h0000000;
+    \208 [302] = 27'h0000000;
+    \208 [303] = 27'h0000000;
+    \208 [304] = 27'h0000000;
+    \208 [305] = 27'h0000000;
+    \208 [306] = 27'h0000000;
+    \208 [307] = 27'h0000000;
+    \208 [308] = 27'h0000000;
+    \208 [309] = 27'h0000000;
+    \208 [310] = 27'h0000000;
+    \208 [311] = 27'h0000000;
+    \208 [312] = 27'h0000000;
+    \208 [313] = 27'h0000000;
+    \208 [314] = 27'h0000000;
+    \208 [315] = 27'h0000000;
+    \208 [316] = 27'h0000000;
+    \208 [317] = 27'h0000000;
+    \208 [318] = 27'h0000000;
+    \208 [319] = 27'h0000000;
+    \208 [320] = 27'h0000000;
+    \208 [321] = 27'h0000000;
+    \208 [322] = 27'h0000000;
+    \208 [323] = 27'h0000000;
+    \208 [324] = 27'h0000000;
+    \208 [325] = 27'h0000000;
+    \208 [326] = 27'h0000000;
+    \208 [327] = 27'h0000000;
+    \208 [328] = 27'h0000000;
+    \208 [329] = 27'h0000000;
+    \208 [330] = 27'h0000000;
+    \208 [331] = 27'h0000000;
+    \208 [332] = 27'h0000000;
+    \208 [333] = 27'h0000000;
+    \208 [334] = 27'h0000000;
+    \208 [335] = 27'h0000000;
+    \208 [336] = 27'h0000000;
+    \208 [337] = 27'h0000000;
+    \208 [338] = 27'h0000000;
+    \208 [339] = 27'h0000000;
+    \208 [340] = 27'h0000000;
+    \208 [341] = 27'h0000000;
+    \208 [342] = 27'h0000000;
+    \208 [343] = 27'h0000000;
+    \208 [344] = 27'h0000000;
+    \208 [345] = 27'h0000000;
+    \208 [346] = 27'h0000000;
+    \208 [347] = 27'h0000000;
+    \208 [348] = 27'h0000000;
+    \208 [349] = 27'h0000000;
+    \208 [350] = 27'h0000000;
+    \208 [351] = 27'h0000000;
+    \208 [352] = 27'h0000000;
+    \208 [353] = 27'h0000000;
+    \208 [354] = 27'h0000000;
+    \208 [355] = 27'h0000000;
+    \208 [356] = 27'h0000000;
+    \208 [357] = 27'h0000000;
+    \208 [358] = 27'h0000000;
+    \208 [359] = 27'h0000000;
+    \208 [360] = 27'h0000000;
+    \208 [361] = 27'h0000000;
+    \208 [362] = 27'h0000000;
+    \208 [363] = 27'h0000000;
+    \208 [364] = 27'h0000000;
+    \208 [365] = 27'h0000000;
+    \208 [366] = 27'h0000000;
+    \208 [367] = 27'h0000000;
+    \208 [368] = 27'h0000000;
+    \208 [369] = 27'h0000000;
+    \208 [370] = 27'h0000000;
+    \208 [371] = 27'h0000000;
+    \208 [372] = 27'h0000000;
+    \208 [373] = 27'h0000000;
+    \208 [374] = 27'h0000000;
+    \208 [375] = 27'h0000000;
+    \208 [376] = 27'h0000000;
+    \208 [377] = 27'h0000000;
+    \208 [378] = 27'h0000000;
+    \208 [379] = 27'h0000000;
+    \208 [380] = 27'h0000000;
+    \208 [381] = 27'h0000000;
+    \208 [382] = 27'h0000000;
+    \208 [383] = 27'h0000000;
+    \208 [384] = 27'h0000000;
+    \208 [385] = 27'h0000000;
+    \208 [386] = 27'h0000000;
+    \208 [387] = 27'h0000000;
+    \208 [388] = 27'h0000000;
+    \208 [389] = 27'h0000000;
+    \208 [390] = 27'h0000000;
+    \208 [391] = 27'h0000000;
+    \208 [392] = 27'h0000000;
+    \208 [393] = 27'h0000000;
+    \208 [394] = 27'h0000000;
+    \208 [395] = 27'h0000000;
+    \208 [396] = 27'h0000000;
+    \208 [397] = 27'h0000000;
+    \208 [398] = 27'h0000000;
+    \208 [399] = 27'h0000000;
+    \208 [400] = 27'h0000000;
+    \208 [401] = 27'h0000000;
+    \208 [402] = 27'h0000000;
+    \208 [403] = 27'h0000000;
+    \208 [404] = 27'h0000000;
+    \208 [405] = 27'h0000000;
+    \208 [406] = 27'h0000000;
+    \208 [407] = 27'h0000000;
+    \208 [408] = 27'h0000000;
+    \208 [409] = 27'h0000000;
+    \208 [410] = 27'h0000000;
+    \208 [411] = 27'h0000000;
+    \208 [412] = 27'h0000000;
+    \208 [413] = 27'h0000000;
+    \208 [414] = 27'h0000000;
+    \208 [415] = 27'h0000000;
+    \208 [416] = 27'h0000000;
+    \208 [417] = 27'h0000000;
+    \208 [418] = 27'h0000000;
+    \208 [419] = 27'h0000000;
+    \208 [420] = 27'h0000000;
+    \208 [421] = 27'h0000000;
+    \208 [422] = 27'h0000000;
+    \208 [423] = 27'h0000000;
+    \208 [424] = 27'h0000000;
+    \208 [425] = 27'h0000000;
+    \208 [426] = 27'h0000000;
+    \208 [427] = 27'h0000000;
+    \208 [428] = 27'h0000000;
+    \208 [429] = 27'h0000000;
+    \208 [430] = 27'h0000000;
+    \208 [431] = 27'h0000000;
+    \208 [432] = 27'h0000000;
+    \208 [433] = 27'h0000000;
+    \208 [434] = 27'h0000000;
+    \208 [435] = 27'h0000000;
+    \208 [436] = 27'h0000000;
+    \208 [437] = 27'h0000000;
+    \208 [438] = 27'h0000000;
+    \208 [439] = 27'h0000000;
+    \208 [440] = 27'h0000000;
+    \208 [441] = 27'h0000000;
+    \208 [442] = 27'h0000000;
+    \208 [443] = 27'h0000000;
+    \208 [444] = 27'h0000000;
+    \208 [445] = 27'h0000000;
+    \208 [446] = 27'h0000000;
+    \208 [447] = 27'h0000000;
+    \208 [448] = 27'h0000000;
+    \208 [449] = 27'h0000000;
+    \208 [450] = 27'h0000000;
+    \208 [451] = 27'h0000000;
+    \208 [452] = 27'h0000000;
+    \208 [453] = 27'h0000000;
+    \208 [454] = 27'h0000000;
+    \208 [455] = 27'h0000000;
+    \208 [456] = 27'h0000000;
+    \208 [457] = 27'h0000000;
+    \208 [458] = 27'h0000000;
+    \208 [459] = 27'h0000000;
+    \208 [460] = 27'h0000000;
+    \208 [461] = 27'h0000000;
+    \208 [462] = 27'h0000000;
+    \208 [463] = 27'h0000000;
+    \208 [464] = 27'h0000000;
+    \208 [465] = 27'h0000000;
+    \208 [466] = 27'h0000000;
+    \208 [467] = 27'h0000000;
+    \208 [468] = 27'h0000000;
+    \208 [469] = 27'h0000000;
+    \208 [470] = 27'h0000000;
+    \208 [471] = 27'h0000000;
+    \208 [472] = 27'h0000000;
+    \208 [473] = 27'h0000000;
+    \208 [474] = 27'h0000000;
+    \208 [475] = 27'h0000000;
+    \208 [476] = 27'h0000000;
+    \208 [477] = 27'h0000000;
+    \208 [478] = 27'h0000000;
+    \208 [479] = 27'h0000000;
+    \208 [480] = 27'h0000000;
+    \208 [481] = 27'h0000000;
+    \208 [482] = 27'h0000000;
+    \208 [483] = 27'h0000000;
+    \208 [484] = 27'h0000000;
+    \208 [485] = 27'h0000000;
+    \208 [486] = 27'h0000000;
+    \208 [487] = 27'h0000000;
+    \208 [488] = 27'h0000000;
+    \208 [489] = 27'h0000000;
+    \208 [490] = 27'h0000000;
+    \208 [491] = 27'h0000000;
+    \208 [492] = 27'h0000000;
+    \208 [493] = 27'h0000000;
+    \208 [494] = 27'h0000000;
+    \208 [495] = 27'h0000000;
+    \208 [496] = 27'h0000000;
+    \208 [497] = 27'h0000000;
+    \208 [498] = 27'h0000000;
+    \208 [499] = 27'h0000000;
+    \208 [500] = 27'h0000000;
+    \208 [501] = 27'h0000000;
+    \208 [502] = 27'h0000000;
+    \208 [503] = 27'h0000000;
+    \208 [504] = 27'h0000000;
+    \208 [505] = 27'h0000000;
+    \208 [506] = 27'h0000000;
+    \208 [507] = 27'h0000000;
+    \208 [508] = 27'h0000000;
+    \208 [509] = 27'h0000000;
+    \208 [510] = 27'h0000000;
+    \208 [511] = 27'h0000000;
+  end
+  always @(posedge clk) begin
+    \208 [_0_] <= 27'h0000000;
+  end
+  assign _4_ = \208 [_5_];
+  assign out_blank = 1'hz;
+  assign out_hsync = 1'hz;
+  assign out_vsync = 1'hz;
+  assign out_red = 8'hzz;
+  assign out_green = _1_;
+  assign out_blue = _2_;
+endmodule
+
+module pixel_processing(clk, in_blank, in_hsync, in_vsync, in_red, in_green, in_blue, is_interlaced, is_second_field, audio_channel, audio_de, audio_sample, switches, out_blank, out_hsync, out_vsync, out_red, out_green, out_blue);
+  input [2:0] audio_channel;
+  input audio_de;
+  input [23:0] audio_sample;
+  input clk;
+  input in_blank;
+  input [7:0] in_blue;
+  input [7:0] in_green;
+  input in_hsync;
+  input [7:0] in_red;
+  input in_vsync;
+  input is_interlaced;
+  input is_second_field;
+  output out_blank;
+  output [7:0] out_blue;
+  output [7:0] out_green;
+  output out_hsync;
+  output [7:0] out_red;
+  output out_vsync;
+  input [7:0] switches;
+  assign out_blank = 1'hz;
+  assign out_hsync = 1'hz;
+  assign out_vsync = 1'hz;
+  assign out_red = 8'hzz;
+  assign out_green = 8'hzz;
+  assign out_blue = 8'hzz;
+endmodule
diff --git a/testsuite/synth/issue1307/testsuite.sh b/testsuite/synth/issue1307/testsuite.sh
new file mode 100755
index 000000000..08ac20e1a
--- /dev/null
+++ b/testsuite/synth/issue1307/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth edge_enhance.vhd hdmi_design.vhd line_delay.vhd pixel_processing.vhd -e > syn_hdmi_design.vhdl
+
+echo "Test successful"
author	Tristan Gingold <tgingold@free.fr>	2020-05-16 07:29:47 +0200
committer	Tristan Gingold <tgingold@free.fr>	2020-05-16 07:29:47 +0200
commit	b9fc9fbf389a24201d05d649daeac782c864404e (patch)
tree	f5e16c669228196f8db8df9269dde6d5c02dc242 /testsuite/synth/issue1307
parent	96b538b0241921d355382b8403f23d79927dfcae (diff)
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