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author | Tristan Gingold <tgingold@free.fr> | 2020-05-12 19:25:13 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-13 06:01:08 +0200 |
commit | 0678dd8ec738f381f8365e8c1473d070f0ee6b82 (patch) | |
tree | 0454737204f283853e1a14338d00a24ab145e38b /testsuite/synth/issue1302/testcase3.vhdl | |
parent | f74e3804a1aea0634e346f0f6ab47ec9db87a5eb (diff) | |
download | ghdl-0678dd8ec738f381f8365e8c1473d070f0ee6b82.tar.gz ghdl-0678dd8ec738f381f8365e8c1473d070f0ee6b82.tar.bz2 ghdl-0678dd8ec738f381f8365e8c1473d070f0ee6b82.zip |
testsuite/synth: add a test for #1302
Diffstat (limited to 'testsuite/synth/issue1302/testcase3.vhdl')
-rw-r--r-- | testsuite/synth/issue1302/testcase3.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/issue1302/testcase3.vhdl b/testsuite/synth/issue1302/testcase3.vhdl new file mode 100644 index 000000000..48c46af34 --- /dev/null +++ b/testsuite/synth/issue1302/testcase3.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase3 is + generic ( + edge : std_logic := '1' + ); + port ( + clk : in std_logic; + D : in std_logic; + Q : out std_logic + ); +end testcase3; + +architecture behavior of testcase3 is +begin + +tc3: process(clk) + begin + if (clk'event and clk=edge) then + Q <= D; + end if; + end process; + +end behavior; |