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authortmeissner <programming@goodcleanfun.de>2020-05-08 11:17:48 +0200
committertgingold <tgingold@users.noreply.github.com>2020-05-08 17:52:51 +0200
commit423a2dbb9716dd91307d17109fbc53ce24ddf4e3 (patch)
treecde82938a3d3e67ab9574c87e1dbb81f824df5db /testsuite/synth/issue1288
parente2aa330a4c6a03685bd6893b4174473ce53830e8 (diff)
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testsuite/synth, testsuite/gna: add tests for ghdl#1288
Diffstat (limited to 'testsuite/synth/issue1288')
-rw-r--r--testsuite/synth/issue1288/issue.vhdl94
-rwxr-xr-xtestsuite/synth/issue1288/testsuite.sh10
2 files changed, 104 insertions, 0 deletions
diff --git a/testsuite/synth/issue1288/issue.vhdl b/testsuite/synth/issue1288/issue.vhdl
new file mode 100644
index 000000000..849a26c54
--- /dev/null
+++ b/testsuite/synth/issue1288/issue.vhdl
@@ -0,0 +1,94 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity sequencer is
+ generic (
+ seq : string
+ );
+ port (
+ clk : in std_logic;
+ data : out std_logic
+ );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+ signal index : natural := seq'low;
+ signal ch : character;
+
+ function to_bit (a : in character) return std_logic is
+ variable ret : std_logic;
+ begin
+ case a is
+ when '0' | '_' => ret := '0';
+ when '1' | '-' => ret := '1';
+ when others => ret := 'X';
+ end case;
+ return ret;
+ end function to_bit;
+
+begin
+
+
+ process (clk) is
+ begin
+ if rising_edge(clk) then
+ if (index < seq'high) then
+ index <= index + 1;
+ end if;
+ end if;
+ end process;
+
+ ch <= seq(index);
+
+ data <= to_bit(ch);
+
+
+end architecture rtl;
+
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity issue is
+ port (
+ clk : in std_logic
+ );
+end entity issue;
+
+
+architecture psl of issue is
+
+ component sequencer is
+ generic (
+ seq : string
+ );
+ port (
+ clk : in std_logic;
+ data : out std_logic
+ );
+ end component sequencer;
+
+ signal a, b : std_logic;
+
+begin
+
+
+ -- 01234567890
+ SEQ_A : sequencer generic map ("__-_-______") port map (clk, a);
+ SEQ_B : sequencer generic map ("_____-_-___") port map (clk, b);
+
+
+
+ -- All is sensitive to rising edge of clk
+ default clock is rising_edge(clk);
+
+ -- This assertion holds
+ NEXT_EVENT_a : assert always (a -> next_e[3 to 5] (b));
+
+
+end architecture psl; \ No newline at end of file
diff --git a/testsuite/synth/issue1288/testsuite.sh b/testsuite/synth/issue1288/testsuite.sh
new file mode 100755
index 000000000..29460b8df
--- /dev/null
+++ b/testsuite/synth/issue1288/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_analyze issue
+
+clean
+
+echo "Test successful"