testsuite/synth: add more tests for #1273

9 files changed, 238 insertions, 4 deletions

diff --git a/testsuite/synth/issue1273/assert4.vhdl b/testsuite/synth/issue1273/assert4.vhdl
new file mode 100644
index 000000000..65714b893
--- /dev/null
+++ b/testsuite/synth/issue1273/assert4.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert4 is
+  port (v : std_logic_Vector (7 downto 0);
+        en : std_logic;
+        clk : std_logic;
+        res : out std_logic);
+end;
+
+architecture behav of assert4 is
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) and en = '1' then
+      assert v /= x"00";
+      res <= v(0) xor v(1);
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1273/assert5.vhdl b/testsuite/synth/issue1273/assert5.vhdl
new file mode 100644
index 000000000..1caae445a
--- /dev/null
+++ b/testsuite/synth/issue1273/assert5.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert5 is
+  port (v : std_logic_Vector (7 downto 0);
+        en : std_logic;
+        clk : std_logic;
+        rst : std_logic;
+        res : out std_logic);
+end;
+
+architecture behav of assert5 is
+begin
+  process (clk, rst)
+  begin
+    if rst = '1' then
+      res <= '0';
+    elsif rising_edge(clk) and en = '1' then
+      assert v /= x"05";
+      res <= v(0) xor v(1);
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1273/assert6.vhdl b/testsuite/synth/issue1273/assert6.vhdl
new file mode 100644
index 000000000..e10226ac1
--- /dev/null
+++ b/testsuite/synth/issue1273/assert6.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert6 is
+  port (v : std_logic_Vector (7 downto 0);
+        en : std_logic;
+        clk : std_logic;
+        rst : std_logic;
+        res : out std_logic);
+end;
+
+architecture behav of assert6 is
+begin
+  process (clk, rst)
+  begin
+    if rst = '1' then
+      res <= '0';
+    elsif rising_edge(clk) and en = '1' then
+      assert v /= x"05";
+      res <= v(0) xor v(1);
+    else
+      assert v = x"00";
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1273/assert7.vhdl b/testsuite/synth/issue1273/assert7.vhdl
new file mode 100644
index 000000000..d99642854
--- /dev/null
+++ b/testsuite/synth/issue1273/assert7.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert7 is
+  port (v : std_logic_Vector (7 downto 0);
+        en : std_logic;
+        clk : std_logic;
+        rst : std_logic;
+        res : out std_logic);
+end;
+
+architecture behav of assert7 is
+begin
+  process (clk, rst)
+  begin
+    if rst = '1' then
+      res <= '0';
+    elsif rising_edge(clk) and en = '1' then
+      assert v /= x"05";
+      assert v /= x"06";
+      assert v /= x"08";
+      res <= v(0) xor v(1);
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1273/tb_assert3.vhdl b/testsuite/synth/issue1273/tb_assert3.vhdl
index 2ad3d0572..543898ef1 100644
--- a/testsuite/synth/issue1273/tb_assert3.vhdl
+++ b/testsuite/synth/issue1273/tb_assert3.vhdl
@@ -1,4 +1,5 @@
 entity tb_assert3 is
+  generic (with_err : boolean := False);
 end tb_assert3;
 
 library ieee;
@@ -22,10 +23,12 @@ begin
     assert res = 5 severity failure;
 
     --  Trigger an error.
-    en <= '1';
-    v <= b"0000_0010";
-    wait for 1 ns;
-    assert res = 1 severity failure;
+    if with_err then
+      en <= '1';
+      v <= b"0000_0010";
+      wait for 1 ns;
+      assert res = 1 severity failure;
+    end if;
 
     wait;
   end process;
diff --git a/testsuite/synth/issue1273/tb_assert4.vhdl b/testsuite/synth/issue1273/tb_assert4.vhdl
new file mode 100644
index 000000000..1322af021
--- /dev/null
+++ b/testsuite/synth/issue1273/tb_assert4.vhdl
@@ -0,0 +1,56 @@
+entity tb_assert4 is
+  generic (with_err : boolean := False);
+end tb_assert4;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_assert4 is
+  signal v : std_logic_Vector (7 downto 0);
+  signal en : std_logic := '0';
+  signal clk : std_logic;
+  signal res : std_logic;
+begin
+  dut: entity work.assert4
+    port map (v, en, clk, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    en <= '1';
+    v <= b"0010_0000";
+    pulse;
+    assert res = '0' severity failure;
+
+    v <= b"0010_0001";
+    pulse;
+    assert res = '1' severity failure;
+
+    v <= b"0010_0011";
+    pulse;
+    assert res = '0' severity failure;
+
+    v <= b"0010_0010";
+    pulse;
+    assert res = '1' severity failure;
+
+    en <= '0';
+    v <= x"00";
+    pulse;
+    assert res = '1' severity failure;
+    
+    --  Trigger an error.
+    if with_err then
+      en <= '1';
+      pulse;
+    end if;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1273/tb_assert5.vhdl b/testsuite/synth/issue1273/tb_assert5.vhdl
new file mode 100644
index 000000000..9c1d9162f
--- /dev/null
+++ b/testsuite/synth/issue1273/tb_assert5.vhdl
@@ -0,0 +1,66 @@
+entity tb_assert5 is
+  generic (with_err : boolean := False);
+end tb_assert5;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_assert5 is
+  signal v : std_logic_Vector (7 downto 0);
+  signal en : std_logic := '0';
+  signal rst : std_logic;
+  signal clk : std_logic;
+  signal res : std_logic;
+begin
+  dut: entity work.assert5
+    port map (v, en, clk, rst, res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+
+    rst <= '0';
+    en <= '1';
+    v <= b"0010_0000";
+    pulse;
+    assert res = '0' severity failure;
+
+    v <= b"0010_0001";
+    pulse;
+    assert res = '1' severity failure;
+
+    v <= b"0010_0011";
+    pulse;
+    assert res = '0' severity failure;
+
+    v <= b"0010_0010";
+    pulse;
+    assert res = '1' severity failure;
+
+    en <= '0';
+    v <= x"05";
+    pulse;
+    assert res = '1' severity failure;
+
+    rst <= '1';
+    wait for 1 ns;
+    assert res = '0' severity failure;
+
+    --  Trigger an error.
+    if with_err then
+      en <= '1';
+      rst <= '0';
+      pulse;
+    end if;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1273/testsuite.sh b/testsuite/synth/issue1273/testsuite.sh
index 5dceb56ee..9cbb3de27 100755
--- a/testsuite/synth/issue1273/testsuite.sh
+++ b/testsuite/synth/issue1273/testsuite.sh
@@ -5,5 +5,11 @@
 synth_analyze issue
 synth_tb assert2
 synth_tb assert3
+synth_tb assert4
+synth_tb assert5
+synth_failure assert6
+synth_analyze assert7
+
+clean
 
 echo "Test successful"
diff --git a/testsuite/synth/issue1273/vassert.v b/testsuite/synth/issue1273/vassert.v
new file mode 100644
index 000000000..7d8afb61d
--- /dev/null
+++ b/testsuite/synth/issue1273/vassert.v
@@ -0,0 +1,6 @@
+module vassert(input wire clk, input wire [7:0] d, output wire q);
+  always @(posedge clk)  begin
+    assert(d != 8'ha5);
+    q <= ^d;
+  end
+endmodule