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author | Tristan Gingold <tgingold@free.fr> | 2020-04-29 08:24:58 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-29 08:24:58 +0200 |
commit | ba342a67ebf6afc00ea25c3b463d7beb93cd16d2 (patch) | |
tree | 3e9fc6b9c77efebda2479c3d49be39a648deab8c /testsuite/synth/issue1272 | |
parent | 4cdf1cee17b7f06ec188dd0f7136fbad498953cb (diff) | |
download | ghdl-ba342a67ebf6afc00ea25c3b463d7beb93cd16d2.tar.gz ghdl-ba342a67ebf6afc00ea25c3b463d7beb93cd16d2.tar.bz2 ghdl-ba342a67ebf6afc00ea25c3b463d7beb93cd16d2.zip |
testsuite/synth: add test for #1272
Diffstat (limited to 'testsuite/synth/issue1272')
-rw-r--r-- | testsuite/synth/issue1272/issue.vhdl | 12 | ||||
-rwxr-xr-x | testsuite/synth/issue1272/testsuite.sh | 9 |
2 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1272/issue.vhdl b/testsuite/synth/issue1272/issue.vhdl new file mode 100644 index 000000000..3a232d0c9 --- /dev/null +++ b/testsuite/synth/issue1272/issue.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue is + port (clk : std_logic); +end entity issue; + +architecture beh of issue is +begin + --psl default clock is rising_edge (clk); + --psl assert (always (true or true)); +end architecture; diff --git a/testsuite/synth/issue1272/testsuite.sh b/testsuite/synth/issue1272/testsuite.sh new file mode 100755 index 000000000..9c407db39 --- /dev/null +++ b/testsuite/synth/issue1272/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS="--std=08 -fpsl" + +synth issue.vhdl -e > syn_issue.vhdl + +echo "Test successful" |