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authorTristan Gingold <tgingold@free.fr>2020-04-22 18:37:31 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-22 18:37:31 +0200
commitd78d7477758f7212890daabcb53b9e2852a3f41a (patch)
treec7815de817360326372b926e3175776129beef84 /testsuite/synth/issue1238
parentc03407bc98348e08a3ffab8c0e1542c4b52a9ce3 (diff)
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testsuite/synth: add tests for #1238
Diffstat (limited to 'testsuite/synth/issue1238')
-rw-r--r--testsuite/synth/issue1238/multiplexers_3.vhdl21
-rw-r--r--testsuite/synth/issue1238/tb_multiplexers_3.vhdl54
-rw-r--r--testsuite/synth/issue1238/tb_tri.vhdl34
-rwxr-xr-xtestsuite/synth/issue1238/testsuite.sh8
-rw-r--r--testsuite/synth/issue1238/tri.vhdl12
5 files changed, 129 insertions, 0 deletions
diff --git a/testsuite/synth/issue1238/multiplexers_3.vhdl b/testsuite/synth/issue1238/multiplexers_3.vhdl
new file mode 100644
index 000000000..71659cd3f
--- /dev/null
+++ b/testsuite/synth/issue1238/multiplexers_3.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity multiplexers_3 is
+
+ port (di : in std_logic_vector(7 downto 0);
+ sel : in std_logic_vector(7 downto 0);
+ do : out std_logic);
+end multiplexers_3;
+
+architecture archi of multiplexers_3 is
+begin
+ do <= di(0) when sel(0)='0' else 'Z';
+ do <= di(1) when sel(1)='0' else 'Z';
+ do <= di(2) when sel(2)='0' else 'Z';
+ do <= di(3) when sel(3)='0' else 'Z';
+ do <= di(4) when sel(4)='0' else 'Z';
+ do <= di(5) when sel(5)='0' else 'Z';
+ do <= di(6) when sel(6)='0' else 'Z';
+ do <= di(7) when sel(7)='0' else 'Z';
+end archi;
diff --git a/testsuite/synth/issue1238/tb_multiplexers_3.vhdl b/testsuite/synth/issue1238/tb_multiplexers_3.vhdl
new file mode 100644
index 000000000..f105be829
--- /dev/null
+++ b/testsuite/synth/issue1238/tb_multiplexers_3.vhdl
@@ -0,0 +1,54 @@
+entity tb_multiplexers_3 is
+end tb_multiplexers_3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_multiplexers_3 is
+ signal di : std_logic_vector(7 downto 0);
+ signal sel : std_logic_vector(7 downto 0);
+ signal do : std_logic;
+begin
+ dut: entity work.multiplexers_3
+ port map (di, sel, do);
+
+ process
+ begin
+ di <= b"1001_0011";
+ sel <= not b"0000_0000";
+ wait for 1 ns;
+ assert do = 'Z' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0000_0001";
+ wait for 1 ns;
+ assert do = '1' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0000_0001";
+ wait for 1 ns;
+ assert do = '1' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0001_0001";
+ wait for 1 ns;
+ assert do = '1' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0010_0000";
+ wait for 1 ns;
+ assert do = '0' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0110_1100";
+ wait for 1 ns;
+ assert do = '0' severity failure;
+
+ di <= b"1001_0011";
+ sel <= not b"0010_0001";
+ wait for 1 ns;
+ assert do = 'X' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1238/tb_tri.vhdl b/testsuite/synth/issue1238/tb_tri.vhdl
new file mode 100644
index 000000000..b1c24ab5a
--- /dev/null
+++ b/testsuite/synth/issue1238/tb_tri.vhdl
@@ -0,0 +1,34 @@
+entity tb_tri is
+end tb_tri;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_tri is
+ signal i : std_logic;
+ signal en : std_logic;
+ signal o : std_logic;
+begin
+ dut: entity work.tri
+ port map (i, en, o);
+
+ process
+ begin
+ i <= '1';
+ en <= '1';
+ wait for 1 ns;
+ assert o = '1' severity failure;
+
+ i <= '0';
+ en <= '1';
+ wait for 1 ns;
+ assert o = '0' severity failure;
+
+ i <= '1';
+ en <= '0';
+ wait for 1 ns;
+ assert o = 'Z' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1238/testsuite.sh b/testsuite/synth/issue1238/testsuite.sh
new file mode 100755
index 000000000..6e65bdc6d
--- /dev/null
+++ b/testsuite/synth/issue1238/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb tri
+synth_tb multiplexers_3
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1238/tri.vhdl b/testsuite/synth/issue1238/tri.vhdl
new file mode 100644
index 000000000..2432be31f
--- /dev/null
+++ b/testsuite/synth/issue1238/tri.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tri is
+ port (i, en : std_logic;
+ o : out std_logic);
+end tri;
+
+architecture behav of tri is
+begin
+ o <= i when en = '1' else 'Z';
+end behav;