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author | Tristan Gingold <tgingold@free.fr> | 2020-04-16 19:46:56 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-16 20:40:21 +0200 |
commit | 3bff44b2a3bd094ef6b0f69f4548a32250d80d22 (patch) | |
tree | f37e30518adc06bb2953df46a7d9daa7b4250429 /testsuite/synth/issue1231/top.vhdl | |
parent | c35ee25d5465d5c3f542c5d2e4b1e490661c577e (diff) | |
download | ghdl-3bff44b2a3bd094ef6b0f69f4548a32250d80d22.tar.gz ghdl-3bff44b2a3bd094ef6b0f69f4548a32250d80d22.tar.bz2 ghdl-3bff44b2a3bd094ef6b0f69f4548a32250d80d22.zip |
testsuite/synth: add case from #1231
Diffstat (limited to 'testsuite/synth/issue1231/top.vhdl')
-rw-r--r-- | testsuite/synth/issue1231/top.vhdl | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/testsuite/synth/issue1231/top.vhdl b/testsuite/synth/issue1231/top.vhdl new file mode 100644 index 000000000..5292ada0c --- /dev/null +++ b/testsuite/synth/issue1231/top.vhdl @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity SINGLE_SRL is + generic (SRL_WIDTH : integer := 24); + port ( + clk : in std_logic; + inp : in std_logic; + outp : out std_logic); +end SINGLE_SRL; + +architecture beh of SINGLE_SRL is + signal shift_reg : std_logic_vector (SRL_WIDTH-1 downto 0); +begin + assert SRL_WIDTH <= 17 + report "The size of Shift Register exceeds the size of a single SRL" + severity FAILURE; + + process (clk) + begin + if rising_edge(clk) then + shift_reg <= shift_reg (SRL_WIDTH-2 downto 0) & inp; + end if; + end process; + + outp <= shift_reg(SRL_WIDTH-1); +end beh; + +library ieee; +use ieee.std_logic_1164.all; + +entity TOP is + port ( + clk : in std_logic; + inp1, inp2 : in std_logic; + outp1, outp2 : out std_logic); +end TOP; + +architecture beh of TOP is + component SINGLE_SRL is + generic (SRL_WIDTH : integer := 16); + port( + clk : in std_logic; + inp : in std_logic; + outp : out std_logic); + end component; +begin + inst1: SINGLE_SRL + generic map (SRL_WIDTH => 13) + port map( + clk => clk, + inp => inp1, + outp => outp1 ); + inst2: SINGLE_SRL + generic map (SRL_WIDTH => 18) + port map( + clk => clk, + inp => inp2, + outp => outp2 ); +end beh; |