testsuite/synth: add a test for #1220

3 files changed, 83 insertions, 0 deletions

diff --git a/testsuite/synth/issue1220/tb_top.vhdl b/testsuite/synth/issue1220/tb_top.vhdl
new file mode 100644
index 000000000..9b4c5d852
--- /dev/null
+++ b/testsuite/synth/issue1220/tb_top.vhdl
@@ -0,0 +1,46 @@
+entity tb_top is
+end tb_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_top is
+  signal clk : std_logic;
+  signal x, y : std_logic_vector (1 downto 0);
+  signal data : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.top
+    port map (clk, x, y, data);
+
+  process
+    procedure pulse is
+    begin
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+      clk <= '0';
+    end pulse;
+  begin
+    clk <= '0';
+
+    x <= "00";
+    y <= "00";
+    pulse;
+    assert data = "0001" severity failure;
+
+    x <= "10";
+    pulse;
+    assert data = "1110" severity failure;
+
+    y <= "01";
+    pulse;
+    assert data = "1101" severity failure;
+
+    x <= "10";
+    y <= "11";
+    pulse;
+    assert data = "0111" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1220/testsuite.sh b/testsuite/synth/issue1220/testsuite.sh
new file mode 100755
index 000000000..60399a753
--- /dev/null
+++ b/testsuite/synth/issue1220/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb top
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1220/top.vhdl b/testsuite/synth/issue1220/top.vhdl
new file mode 100644
index 000000000..f4cbc38d3
--- /dev/null
+++ b/testsuite/synth/issue1220/top.vhdl
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity top is
+	port(
+		clock : in std_logic;
+		x : in std_logic_vector(1 downto 0);
+		y : in std_logic_vector(1 downto 0);
+		data : out std_logic_vector(3 downto 0)
+	);
+end entity;
+
+architecture arch of top is
+
+	type rom_t is array(0 to 3, 0 to 3) of std_logic_vector(3 downto 0);
+	constant rom : rom_t := (
+		("0001", "0010", "0100", "1000"),
+		("0011", "0110", "1100", "1001"),
+		("1110", "1101", "1011", "0111"),
+		("0000", "1111", "1111", "0000")
+	);
+begin
+	process (clock)
+	begin
+		if rising_edge(clock) then
+			data <= rom(to_integer(unsigned(x)), to_integer(unsigned(y)));
+		end if;
+	end process;
+end architecture;