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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-13 07:08:43 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-13 07:08:43 +0200 |
| commit | 5942e39d7768e432fb7394c66b11fdbd092ae78e (patch) | |
| tree | e505450affb44dba8011966f3c0c1620aea52763 /testsuite/synth/issue1218/top.vhdl | |
| parent | 5ed51a3a905c0096930c2b1c66932df24468dba9 (diff) | |
| download | ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.tar.gz ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.tar.bz2 ghdl-5942e39d7768e432fb7394c66b11fdbd092ae78e.zip | |
testsuite/synth: add a test for #1218
Diffstat (limited to 'testsuite/synth/issue1218/top.vhdl')
| -rw-r--r-- | testsuite/synth/issue1218/top.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/issue1218/top.vhdl b/testsuite/synth/issue1218/top.vhdl new file mode 100644 index 000000000..b9169a28f --- /dev/null +++ b/testsuite/synth/issue1218/top.vhdl @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity top is +port ( + ch : in integer range 0 to 7; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0) +); +end entity; + +architecture arch of top is +begin + dout <= din srl (ch + 1); +end architecture; |