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authorTristan Gingold <tgingold@free.fr>2020-04-11 15:37:27 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-11 15:37:27 +0200
commitbc269c6a47da7aaefb0bfb85cea3ad08447ab1b0 (patch)
tree5df4df6b52ecefb61840de9457a460294241f55e /testsuite/synth/issue1210
parent163a3c210504373b3348c4d9ddfad0ee19439f6b (diff)
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testsuite/synth: add a test for #1210
Diffstat (limited to 'testsuite/synth/issue1210')
-rw-r--r--testsuite/synth/issue1210/bug.vhdl15
-rwxr-xr-xtestsuite/synth/issue1210/testsuite.sh7
2 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue1210/bug.vhdl b/testsuite/synth/issue1210/bug.vhdl
new file mode 100644
index 000000000..2bd385609
--- /dev/null
+++ b/testsuite/synth/issue1210/bug.vhdl
@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.math_real.all;
+
+entity bug is
+ port (
+ dummy : in std_ulogic
+ );
+end entity;
+
+architecture rtl of bug is
+ constant a : real := floor(15.0/4.0);
+ constant b : real := ceil(15.0/4.0);
+begin
+end architecture;
diff --git a/testsuite/synth/issue1210/testsuite.sh b/testsuite/synth/issue1210/testsuite.sh
new file mode 100755
index 000000000..6f3c0d0e6
--- /dev/null
+++ b/testsuite/synth/issue1210/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth bug.vhdl -e > syn_bug.vhdl
+
+echo "Test successful"