testsuite/synth: add case for #1176

2 files changed, 33 insertions, 0 deletions

diff --git a/testsuite/synth/issue1176/issue.vhdl b/testsuite/synth/issue1176/issue.vhdl
new file mode 100644
index 000000000..d732dca49
--- /dev/null
+++ b/testsuite/synth/issue1176/issue.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity issue is
+    port (clock : in  std_logic;
+            bar : out signed(8-1 downto 0));
+end issue;
+
+architecture rtl of issue is
+begin
+
+    process (clock)
+        variable foo : signed(8-1 downto 0);
+    begin
+        if rising_edge(clock) then
+            foo := (others=>'0');
+            foo := foo + 1;
+        end if;
+
+        bar <= foo;
+    end process;
+
+end architecture;
+
diff --git a/testsuite/synth/issue1176/testsuite.sh b/testsuite/synth/issue1176/testsuite.sh
new file mode 100755
index 000000000..30f40648a
--- /dev/null
+++ b/testsuite/synth/issue1176/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze issue
+clean
+
+echo "Test successful"