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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:58:28 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-23 06:58:28 +0100 |
| commit | f4e8faae688d96a9bf072b95d9e29dce84bd3271 (patch) | |
| tree | dede654e73781e846ded433c6b38448dd63dbb0e /testsuite/synth/issue1169 | |
| parent | cb648989d0a900dd639cd93bc338d4165441ff2b (diff) | |
| download | ghdl-f4e8faae688d96a9bf072b95d9e29dce84bd3271.tar.gz ghdl-f4e8faae688d96a9bf072b95d9e29dce84bd3271.tar.bz2 ghdl-f4e8faae688d96a9bf072b95d9e29dce84bd3271.zip | |
testsuite/synth: add a test for #1169
Diffstat (limited to 'testsuite/synth/issue1169')
| -rw-r--r-- | testsuite/synth/issue1169/bug.vhdl | 24 | ||||
| -rwxr-xr-x | testsuite/synth/issue1169/testsuite.sh | 8 |
2 files changed, 32 insertions, 0 deletions
diff --git a/testsuite/synth/issue1169/bug.vhdl b/testsuite/synth/issue1169/bug.vhdl new file mode 100644 index 000000000..d843b770e --- /dev/null +++ b/testsuite/synth/issue1169/bug.vhdl @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port( + dummy : in std_ulogic + ); +end bug; + +architecture behav of bug is + constant VALUES_END : positive := 1; + constant ARRAY_LENGTH : positive := 16; + + subtype value_t is integer range 0 to VALUES_END-1; + type array_t is array (0 to ARRAY_LENGTH-1) of value_t; + + signal idx : integer range 0 to ARRAY_LENGTH-1; + signal value : value_t; + + signal array_v : array_t; +begin + array_v(idx) <= value; +end architecture; diff --git a/testsuite/synth/issue1169/testsuite.sh b/testsuite/synth/issue1169/testsuite.sh new file mode 100755 index 000000000..121ca9a6a --- /dev/null +++ b/testsuite/synth/issue1169/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_analyze bug +clean + +echo "Test successful" |