testsuite/synth: add a test for #1164

2 files changed, 36 insertions, 0 deletions

diff --git a/testsuite/synth/issue1164/bug.vhdl b/testsuite/synth/issue1164/bug.vhdl
new file mode 100644
index 000000000..a0b9ac969
--- /dev/null
+++ b/testsuite/synth/issue1164/bug.vhdl
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+	port(
+		clk                     :  in std_ulogic;
+		reset_n                 :  in std_ulogic
+	);
+end bug;
+
+architecture behav of bug is
+	component comp is
+	port (		
+		data : in std_ulogic_vector
+	);
+	end component;
+	
+	type fifo_rdata_t is array (0 to 0) of std_ulogic_vector(4*8-1 downto 0);
+	signal fifo_rdata : fifo_rdata_t;
+begin
+	c : comp
+	port map(
+		data => fifo_rdata(0)
+	);
+end architecture;
+
diff --git a/testsuite/synth/issue1164/testsuite.sh b/testsuite/synth/issue1164/testsuite.sh
new file mode 100755
index 000000000..2be3b2f1a
--- /dev/null
+++ b/testsuite/synth/issue1164/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze bug
+
+clean
+
+echo "Test successful"