testsuite/synth: add test case for #1140

3 files changed, 118 insertions, 0 deletions

diff --git a/testsuite/synth/issue1140/ent.vhdl b/testsuite/synth/issue1140/ent.vhdl
new file mode 100644
index 000000000..1713d3901
--- /dev/null
+++ b/testsuite/synth/issue1140/ent.vhdl
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+	generic (NUM_CHANNELS : natural := 4);
+	port (
+		iar   : in  unsigned(15 downto 0);
+		ipend : in  unsigned(NUM_CHANNELS-1 downto 0);
+		irq   : out unsigned(3 downto 0);
+		clk   : in std_logic
+	);
+end;
+
+architecture a of ent is
+	type irq_t is
+		array (integer range 0 to 4-1) of unsigned(NUM_CHANNELS-1 downto 0);
+
+	signal imap : irq_t;
+
+	function or_reduce (v: in unsigned) return std_logic is
+		variable rv : std_logic := '0';
+	begin
+		for i in v'range loop
+			rv := rv or v(i);
+		end loop;
+		return rv;
+	end function;
+
+
+begin
+
+gen_irqmap:
+  for i in 0 to 4-1 generate
+	irq(i) <= or_reduce(imap(i));
+  end generate;
+
+irq_map:
+	process (clk)
+		variable itmp : irq_t := (others => (others => '0'));
+	begin
+		-- IRQ channel assignment:
+		if rising_edge(clk) then
+			for i in 0 to NUM_CHANNELS-1 loop
+				itmp(to_integer(iar(i*2+1 downto i*2)))(i) := ipend(i);
+			end loop;
+			imap <= itmp;
+		end if;
+	end process;
+end;
+
diff --git a/testsuite/synth/issue1140/tb_ent.vhdl b/testsuite/synth/issue1140/tb_ent.vhdl
new file mode 100644
index 000000000..85d370e2e
--- /dev/null
+++ b/testsuite/synth/issue1140/tb_ent.vhdl
@@ -0,0 +1,49 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_ent is
+	-- Interrupt mapping register:
+	signal iar	 : unsigned(15 downto 0) := "0000000010010000";
+	signal ipend : unsigned(3 downto 0) := (others => '0');
+	signal irq : unsigned(3 downto 0);
+	signal clk : std_logic := '0';
+begin
+	dut: entity work.ent
+	generic map (NUM_CHANNELS => 4)
+		port map (iar => iar, ipend => ipend, irq => irq, clk => clk);
+
+	process
+	begin
+		clk <= not clk;
+		wait for 1 ns;
+	end process;
+
+stim:
+	process
+	begin
+		wait for 10 ns;
+		ipend(0) <= '1';
+		wait for 10 ns;
+		ipend(1) <= '1';
+		wait for 10 ns;
+		ipend(2) <= '1';
+		wait for 10 ns;
+		ipend <= (others => '0');
+
+		wait for 10 ns;
+		ipend(3) <= '1';
+		wait for 10 ns;
+		ipend(2) <= '1';
+		wait for 10 ns;
+		ipend(1) <= '1';
+		wait for 10 ns;
+		ipend <= (others => '0');
+
+		wait;
+	end process;
+
+end behav;
diff --git a/testsuite/synth/issue1140/testsuite.sh b/testsuite/synth/issue1140/testsuite.sh
new file mode 100755
index 000000000..feb3c77fd
--- /dev/null
+++ b/testsuite/synth/issue1140/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --stop-time=10us
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0 --stop-time=10us
+    clean
+done
+
+echo "Test successful"