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authorTristan Gingold <tgingold@free.fr>2020-02-18 18:44:01 +0100
committerTristan Gingold <tgingold@free.fr>2020-02-18 18:44:01 +0100
commit3689e0eb1d8b4a9689afa6f76187f1ecdc5ec458 (patch)
tree77766bd7f22aaa0543872316060cc28a3cd66731 /testsuite/synth/issue1139/ent.vhdl
parentd77dd8c6d657e447d3931d33c8ce5b637fbda758 (diff)
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testsuite/synth: add test for #1139
Diffstat (limited to 'testsuite/synth/issue1139/ent.vhdl')
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diff --git a/testsuite/synth/issue1139/ent.vhdl b/testsuite/synth/issue1139/ent.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity child is
+ port (
+ x : in std_logic;
+ y : out std_logic
+ );
+end;
+
+architecture a of child is
+begin
+ y <= x;
+end;
+
+-----------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (
+ a : in std_logic;
+ b : in std_logic;
+ q : out std_logic
+ );
+end;
+
+architecture a of ent is
+ component child_comp is
+ port (
+ x : in std_logic;
+ y : out std_logic
+ );
+ end component;
+begin
+ child_inst: child_comp
+ port map (
+ x => a and b,
+ y => q
+ );
+end;
+
+-----------------------------------
+
+configuration conf of ent is
+ for a
+ for child_inst : child_comp
+ use entity work.child;
+ end for;
+ end for;
+end configuration;