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author | Tristan Gingold <tgingold@free.fr> | 2020-02-02 19:38:39 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-02 19:38:39 +0100 |
commit | 55faf476ebc08240e9052d184221b57092e68db9 (patch) | |
tree | 0ca5fbfd27894127e0d5a5e9caffdfd3ccfd1dd8 /testsuite/synth/issue1117/ent.vhdl | |
parent | 592e6beefd3f15f86dbc99102d6f71039ff63591 (diff) | |
download | ghdl-55faf476ebc08240e9052d184221b57092e68db9.tar.gz ghdl-55faf476ebc08240e9052d184221b57092e68db9.tar.bz2 ghdl-55faf476ebc08240e9052d184221b57092e68db9.zip |
testsuite/synth: add test for #1117
Diffstat (limited to 'testsuite/synth/issue1117/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1117/ent.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/synth/issue1117/ent.vhdl b/testsuite/synth/issue1117/ent.vhdl new file mode 100644 index 000000000..135d2d31c --- /dev/null +++ b/testsuite/synth/issue1117/ent.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity ent is + generic ( + G : unsigned(31 downto 0) + ); + port ( + res : out unsigned (31 downto 0)); +end; + +architecture a of ent is +begin + res <= g; +end; |