testsuite/synth: add a test for #1082

3 files changed, 50 insertions, 1 deletions

diff --git a/testsuite/synth/issue1082/tb_test.vhdl b/testsuite/synth/issue1082/tb_test.vhdl
new file mode 100644
index 000000000..b109cd534
--- /dev/null
+++ b/testsuite/synth/issue1082/tb_test.vhdl
@@ -0,0 +1,21 @@
+entity tb_test is
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_test is
+  signal a : std_logic_vector (31 downto 0) := (others => '0');
+  signal b : std_logic_vector (31 downto 0);
+begin
+  dut: entity work.test
+    port map (a_in => a, b_out => b);
+
+  process
+  begin
+    a <= x"0000_0003";
+    wait for 1 ns;
+    assert b = x"0000_0007" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1082/test.vhdl b/testsuite/synth/issue1082/test.vhdl
new file mode 100644
index 000000000..00d843092
--- /dev/null
+++ b/testsuite/synth/issue1082/test.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+    port(
+	a_in     : in  std_logic_vector(31 downto 0);
+	b_out     : out  std_logic_vector(31 downto 0)
+	);
+end test;
+
+architecture rtl of test is
+begin
+    process(all)
+    begin
+      b_out <= std_logic_vector
+               (to_unsigned((31-to_integer(unsigned(a_in))) / 4, 32));
+    end process;
+end;
diff --git a/testsuite/synth/issue1082/testsuite.sh b/testsuite/synth/issue1082/testsuite.sh
index 26a25c13f..cca8f9080 100755
--- a/testsuite/synth/issue1082/testsuite.sh
+++ b/testsuite/synth/issue1082/testsuite.sh
@@ -4,6 +4,15 @@
 
 GHDL_STD_FLAGS=--std=08
 
-synth ent.vhdl -e
+for t in test; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
 
 echo "Test successful"