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author | Tristan Gingold <tgingold@free.fr> | 2023-04-17 09:05:20 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-17 09:06:42 +0200 |
commit | 5c0ea8c8b107c5f0be4dff9fbc5d31c43b592b3d (patch) | |
tree | 43121cf7a70052c4839c3f99fc4bc839c97c94c7 /testsuite/synth/issue1079/tb_test2n.vhdl | |
parent | 87eb11eb6ece74a248ebcf32d21322f467108ca1 (diff) | |
download | ghdl-5c0ea8c8b107c5f0be4dff9fbc5d31c43b592b3d.tar.gz ghdl-5c0ea8c8b107c5f0be4dff9fbc5d31c43b592b3d.tar.bz2 ghdl-5c0ea8c8b107c5f0be4dff9fbc5d31c43b592b3d.zip |
testsuite/synth: add test for previous commit
Diffstat (limited to 'testsuite/synth/issue1079/tb_test2n.vhdl')
-rw-r--r-- | testsuite/synth/issue1079/tb_test2n.vhdl | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/testsuite/synth/issue1079/tb_test2n.vhdl b/testsuite/synth/issue1079/tb_test2n.vhdl new file mode 100644 index 000000000..90f975f1c --- /dev/null +++ b/testsuite/synth/issue1079/tb_test2n.vhdl @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_test2n is +end; + +architecture behav of tb_test2n is + signal clk : std_logic; + signal rd_addr : std_logic_vector(7 downto 0); + signal rd_data : std_logic_vector(63 downto 0); + signal en : std_logic; + signal wr_sel : std_logic_vector(7 downto 0); + signal wr_addr : std_logic_vector(7 downto 0); + signal wr_data : std_logic_vector(63 downto 0); +begin + inst_test2n: entity work.test2n + port map ( + clk => clk, + en => en, + rd_addr => rd_addr, + rd_data => rd_data, + wr_sel => wr_sel, + wr_addr => wr_addr, + wr_data => wr_data); + + process + procedure pulse is + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end pulse; + begin + en <= '0'; + wr_sel <= x"ff"; + pulse; + + en <= '1'; + wr_addr <= x"01"; + wr_data <= x"01_12_34_56_78_9a_bc_de"; + pulse; + + wr_addr <= x"02"; + wr_data <= x"02_12_34_56_78_9a_bc_de"; + + rd_addr <= x"01"; + pulse; + + assert rd_data = x"01_12_34_56_78_9a_bc_de"; + wait; + end process; +end behav; |