testsuite/synth: add a test for #1076

4 files changed, 156 insertions, 1 deletions

diff --git a/testsuite/synth/issue1076/ent2.vhdl b/testsuite/synth/issue1076/ent2.vhdl
new file mode 100644
index 000000000..ca10c2e4a
--- /dev/null
+++ b/testsuite/synth/issue1076/ent2.vhdl
@@ -0,0 +1,68 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+	-- This case works.
+	-- generic ( CONFIG_C1: boolean := false );
+	port (
+		i   : in std_logic;
+		o   : out std_logic;
+		q   : out std_logic
+	);
+        constant CONFIG_C1 : boolean := false;
+end;
+
+architecture a of ent2 is
+   component c1 is
+	port (i: in std_logic; o   : out std_logic);
+   end component;
+
+   component c2 is
+	port (i: in std_logic; o   : out std_logic);
+   end component;
+begin
+	gen: if false generate
+		o <= '1';
+	else generate
+		o <= '0';
+	end generate;
+
+maybe_c1:
+	if CONFIG_C1 generate
+	c1_inst: c1 port map (i => i, o=> q);
+	end generate;
+
+maybe_c2:
+	if not CONFIG_C1 generate
+	c2_inst: c2 port map (i => i, o=> q);
+	end generate;
+		
+
+end;
+
+-- Added entities to satisfy simulation:
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity c1 is
+	port (i: in std_logic; o   : out std_logic);
+end entity;
+
+architecture a of c1 is
+begin
+	o <= i;
+end a;
+	
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity c2 is
+	port (i: in std_logic; o   : out std_logic);
+end entity;
+
+architecture a of c2 is
+begin
+	o <= i;
+end a;
+
diff --git a/testsuite/synth/issue1076/ent3.vhdl b/testsuite/synth/issue1076/ent3.vhdl
new file mode 100644
index 000000000..fd81a9ca9
--- /dev/null
+++ b/testsuite/synth/issue1076/ent3.vhdl
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+	use work.ext_comp.all;
+
+entity ent is
+	-- This case works.
+	-- generic ( CONFIG_C1: boolean := false );
+	port (
+		i   : in std_logic;
+		o   : out std_logic;
+		q   : out std_logic
+	);
+        constant CONFIG_C1 : boolean := false;
+end;
+
+architecture a of ent is
+
+begin
+	gen: if false generate
+		o <= '1';
+	else generate
+		o <= '0';
+	end generate;
+
+maybe_c1:
+	if CONFIG_C1 generate
+	c1_inst: c1 port map (i => i, o=> q);
+	end generate;
+
+maybe_c2:
+	if not CONFIG_C1 generate
+	c2_inst: c2 port map (i => i, o=> q);
+	end generate;
+		
+
+end;
+
+-- Added entities to satisfy simulation:
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity c1 is
+	port (i: in std_logic; o   : out std_logic);
+end entity;
+
+architecture a of c1 is
+begin
+	o <= i;
+end a;
+	
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity c2 is
+	port (i: in std_logic; o   : out std_logic);
+end entity;
+
+architecture a of c2 is
+begin
+	o <= i;
+end a;
+
diff --git a/testsuite/synth/issue1076/tb_ent2.vhdl b/testsuite/synth/issue1076/tb_ent2.vhdl
new file mode 100644
index 000000000..42cc0b6b2
--- /dev/null
+++ b/testsuite/synth/issue1076/tb_ent2.vhdl
@@ -0,0 +1,22 @@
+entity tb_ent2 is
+end tb_ent2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent2 is
+  signal i   : std_logic;
+  signal a   : std_logic;
+  signal b   : std_logic;
+begin
+  dut: entity work.ent2
+    port map (i => i, o => a, q => b);
+
+  process
+  begin
+    
+    wait for 1 ns;
+    assert a = '0' severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1076/testsuite.sh b/testsuite/synth/issue1076/testsuite.sh
index f24786843..4593a0d74 100755
--- a/testsuite/synth/issue1076/testsuite.sh
+++ b/testsuite/synth/issue1076/testsuite.sh
@@ -4,7 +4,7 @@
 
 GHDL_STD_FLAGS=--std=08
 
-for t in ent; do
+for t in ent ent2; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean