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authorTristan Gingold <tgingold@free.fr>2020-01-02 10:04:58 +0100
committerTristan Gingold <tgingold@free.fr>2020-01-02 10:04:58 +0100
commit46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4 (patch)
tree1725b07d0aaff46d008506c2a2d6b2aea8f05a69 /testsuite/synth/issue1064/test.vhdl
parentd56c58668b10ca7a6684cb518b4978207c7b88b2 (diff)
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testsuite/synth: add a test for #1064
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diff --git a/testsuite/synth/issue1064/test.vhdl b/testsuite/synth/issue1064/test.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+ port (i : std_ulogic;
+ o : out std_ulogic);
+end entity test;
+
+architecture behaviour of test is
+ procedure zot(e: inout std_ulogic) is
+ begin
+ e := '0';
+ end;
+
+begin
+ execute1_1: process(all)
+ variable blah: std_ulogic;
+ begin
+ blah := i;
+ zot(blah);
+ o <= blah;
+ end process;
+end architecture behaviour;