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author | Tristan Gingold <tgingold@free.fr> | 2020-01-02 10:04:58 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-02 10:04:58 +0100 |
commit | 46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4 (patch) | |
tree | 1725b07d0aaff46d008506c2a2d6b2aea8f05a69 /testsuite/synth/issue1064/test.vhdl | |
parent | d56c58668b10ca7a6684cb518b4978207c7b88b2 (diff) | |
download | ghdl-46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4.tar.gz ghdl-46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4.tar.bz2 ghdl-46f881b0ad6a674bdb92ca8549ac71f4b8f9b6a4.zip |
testsuite/synth: add a test for #1064
Diffstat (limited to 'testsuite/synth/issue1064/test.vhdl')
-rw-r--r-- | testsuite/synth/issue1064/test.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue1064/test.vhdl b/testsuite/synth/issue1064/test.vhdl new file mode 100644 index 000000000..7895a602c --- /dev/null +++ b/testsuite/synth/issue1064/test.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is + port (i : std_ulogic; + o : out std_ulogic); +end entity test; + +architecture behaviour of test is + procedure zot(e: inout std_ulogic) is + begin + e := '0'; + end; + +begin + execute1_1: process(all) + variable blah: std_ulogic; + begin + blah := i; + zot(blah); + o <= blah; + end process; +end architecture behaviour; |