testsuite/synth: add test for #1058

3 files changed, 61 insertions, 0 deletions

diff --git a/testsuite/synth/issue1058/ent.vhdl b/testsuite/synth/issue1058/ent.vhdl
new file mode 100644
index 000000000..b636b4780
--- /dev/null
+++ b/testsuite/synth/issue1058/ent.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+	port (
+		clk : in std_logic;
+		o   : out std_logic_vector(31 downto 0)
+	);
+end ent;
+
+architecture a of ent is
+begin
+	process(clk)
+		variable var : std_logic_vector(31 downto 0);
+	begin
+		if rising_edge(clk) then
+			var := x"0000_0000";
+			o <= x"8000_0000" or var;
+		end if;
+	end process;
+end a;
+
diff --git a/testsuite/synth/issue1058/tb_ent.vhdl b/testsuite/synth/issue1058/tb_ent.vhdl
new file mode 100644
index 000000000..10391f98c
--- /dev/null
+++ b/testsuite/synth/issue1058/tb_ent.vhdl
@@ -0,0 +1,23 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal clk : std_logic;
+  signal v : std_logic_vector (31 downto 0);
+begin
+  dut: entity work.ent
+    port map (clk => clk, o => v);
+
+  process
+  begin
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+    assert v = x"8000_0000" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1058/testsuite.sh b/testsuite/synth/issue1058/testsuite.sh
new file mode 100755
index 000000000..e30a741e0
--- /dev/null
+++ b/testsuite/synth/issue1058/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"