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author | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:01:07 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:01:07 +0100 |
commit | 0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00 (patch) | |
tree | 3b5635767bb6139542a954e1c17728908141c219 /testsuite/synth/issue1054/tb_simple01.vhdl | |
parent | e0a1519e89fbc896517ced756719679e223c5401 (diff) | |
download | ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.tar.gz ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.tar.bz2 ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.zip |
testsuite/synth: add testcase for #1054
Diffstat (limited to 'testsuite/synth/issue1054/tb_simple01.vhdl')
-rw-r--r-- | testsuite/synth/issue1054/tb_simple01.vhdl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/issue1054/tb_simple01.vhdl b/testsuite/synth/issue1054/tb_simple01.vhdl new file mode 100644 index 000000000..7858db0bc --- /dev/null +++ b/testsuite/synth/issue1054/tb_simple01.vhdl @@ -0,0 +1,30 @@ +entity tb_simple01 is +end tb_simple01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_simple01 is + signal a : std_logic; + signal b : std_logic; + signal c : std_logic; + signal z : std_logic; +begin + dut: entity work.simple01 + port map (a, b, c, z); + + process + constant bv : std_logic_vector := b"0111"; + constant cv : std_logic_vector := b"0011"; + constant zv : std_logic_vector := b"0111"; + begin + a <= '0'; + for i in bv'range loop + b <= bv (i); + c <= cv (i); + wait for 1 ns; + assert z = zv(i) severity failure; + end loop; + wait; + end process; +end behav; |