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authorTristan Gingold <tgingold@free.fr>2019-11-29 19:09:13 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-29 19:09:13 +0100
commit75d82a9f92a1845ae933d2599cddf92f938446af (patch)
tree5a5f9c2c1b3b0a5cb54dee204562aa19d5603050 /testsuite/synth/issue1046
parent09de5ec9c9e8c66b2690c53b4e89ce81c5d447e5 (diff)
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testsuite: add case for #1046
Diffstat (limited to 'testsuite/synth/issue1046')
-rw-r--r--testsuite/synth/issue1046/concat01.vhdl14
-rw-r--r--testsuite/synth/issue1046/tb_concat01.vhdl20
-rwxr-xr-xtestsuite/synth/issue1046/testsuite.sh16
3 files changed, 50 insertions, 0 deletions
diff --git a/testsuite/synth/issue1046/concat01.vhdl b/testsuite/synth/issue1046/concat01.vhdl
new file mode 100644
index 000000000..12f817d8d
--- /dev/null
+++ b/testsuite/synth/issue1046/concat01.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat01 is
+ generic (a : std_logic_vector (7 downto 0) := x"ab";
+ b : std_logic_vector (7 downto 0) := x"9e");
+ port (res : out std_logic_vector (15 downto 0));
+end concat01;
+
+architecture behav of concat01 is
+ constant c : std_logic_vector := a & b;
+begin
+ res <= c;
+end behav;
diff --git a/testsuite/synth/issue1046/tb_concat01.vhdl b/testsuite/synth/issue1046/tb_concat01.vhdl
new file mode 100644
index 000000000..1c6f25cc2
--- /dev/null
+++ b/testsuite/synth/issue1046/tb_concat01.vhdl
@@ -0,0 +1,20 @@
+entity tb_concat01 is
+end tb_concat01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_concat01 is
+ signal a : std_logic_vector(15 downto 0);
+begin
+ dut: entity work.concat01
+ port map (a);
+
+ process
+ begin
+ wait for 1 ns;
+ assert a = x"ab9e" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1046/testsuite.sh b/testsuite/synth/issue1046/testsuite.sh
new file mode 100755
index 000000000..0ad6d0e90
--- /dev/null
+++ b/testsuite/synth/issue1046/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in concat01; do
+ analyze $t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t
+ clean
+
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl tb_$t.vhdl
+ elab_simulate tb_$t --ieee-asserts=disable-at-0
+ clean
+done
+
+echo "Test successful"