testsuite/synth: add testcase for #1025

3 files changed, 86 insertions, 0 deletions

diff --git a/testsuite/synth/issue1025/ent.vhdl b/testsuite/synth/issue1025/ent.vhdl
new file mode 100644
index 000000000..ef2a39002
--- /dev/null
+++ b/testsuite/synth/issue1025/ent.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+  port (
+    rst : std_logic;
+		clk : in std_logic;
+		counter : out natural
+	);
+end entity;
+
+architecture a of ent is
+	procedure incr(signal i : inout natural) is
+	begin
+		i <= i + 1;
+	end procedure;
+begin
+	process(clk)
+	begin
+          if rising_edge(clk) then
+            if rst = '1' then
+              counter <= 0;
+            else
+              -- works:
+              --counter <= counter + 1;
+              incr(counter);
+            end if;
+          end if;
+	end process;
+end;
diff --git a/testsuite/synth/issue1025/tb_ent.vhdl b/testsuite/synth/issue1025/tb_ent.vhdl
new file mode 100644
index 000000000..30ead5166
--- /dev/null
+++ b/testsuite/synth/issue1025/tb_ent.vhdl
@@ -0,0 +1,39 @@
+entity tb_ent is
+end tb_ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ent is
+  signal clk : std_logic;
+  signal counter : natural;
+  signal rst : std_logic;
+begin
+  dut: entity work.ent
+    port map (
+      rst => rst,
+      clk => clk,
+      counter => counter);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert counter = 0 severity failure;
+    rst <= '0';
+    pulse;
+    assert counter = 1 severity failure;
+    pulse;
+    assert counter = 2 severity failure;
+    pulse;
+    assert counter = 3 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1025/testsuite.sh b/testsuite/synth/issue1025/testsuite.sh
new file mode 100755
index 000000000..9cf76ccac
--- /dev/null
+++ b/testsuite/synth/issue1025/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"