testsuite/synth: add testcase for #1014

3 files changed, 66 insertions, 0 deletions

diff --git a/testsuite/synth/issue1014/record_test.vhdl b/testsuite/synth/issue1014/record_test.vhdl
new file mode 100644
index 000000000..9362d7c4a
--- /dev/null
+++ b/testsuite/synth/issue1014/record_test.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity record_test is
+  port (
+    o : out integer
+  );
+end record_test;
+
+architecture rtl of record_test is
+  type t_record is record
+    int  : integer;
+  end record t_record;
+
+  function get_constants(choice : std_logic) return t_record is
+    variable v_const : t_record;
+  begin
+    if choice = '0' then
+      v_const := (int => 27.777 us / 83.333 ns);
+    elsif choice = '1' then
+      v_const := (int => 26.316 us / 83.333 ns);
+    end if;
+    return v_const;
+  end function get_constants;
+
+  constant rec_constant : t_record := get_constants('0');
+  signal int_test : integer range 0 to rec_constant.int := 0;
+  signal slv_test : std_logic_vector(rec_constant.int downto 0) := (others => '0');
+begin
+  o <= rec_constant.int;
+end rtl;
diff --git a/testsuite/synth/issue1014/tb_record_test.vhdl b/testsuite/synth/issue1014/tb_record_test.vhdl
new file mode 100644
index 000000000..e9fd6e06d
--- /dev/null
+++ b/testsuite/synth/issue1014/tb_record_test.vhdl
@@ -0,0 +1,19 @@
+entity tb_record_test is
+end tb_record_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_record_test is
+  signal v : integer;
+begin
+  dut: entity work.record_test
+    port map (o => v);
+
+  process
+  begin
+    wait for 1 ns;
+    assert v = 333 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1014/testsuite.sh b/testsuite/synth/issue1014/testsuite.sh
new file mode 100755
index 000000000..5acecf2a9
--- /dev/null
+++ b/testsuite/synth/issue1014/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in record_test; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"