testsuite/synth: add a test for previous commit.

3 files changed, 51 insertions, 1 deletions

diff --git a/testsuite/synth/if01/if02.vhdl b/testsuite/synth/if01/if02.vhdl
new file mode 100644
index 000000000..53fee6864
--- /dev/null
+++ b/testsuite/synth/if01/if02.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity if02 is
+  port (c : std_logic_vector(7 downto 0);
+        s : std_logic;
+        r : out std_logic_vector(7 downto 0));
+end if02;
+
+architecture behav of if02 is
+begin
+  process (c, s)
+  begin
+    if s = '0' then
+      r (6 downto 0) <= c (7 downto 1);
+      r (7) <= c (0);
+    else
+      r (0) <= c (7);
+      r (7 downto 1) <= c (6 downto 0);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/if01/tb_if02.vhdl b/testsuite/synth/if01/tb_if02.vhdl
new file mode 100644
index 000000000..977aa64e8
--- /dev/null
+++ b/testsuite/synth/if01/tb_if02.vhdl
@@ -0,0 +1,28 @@
+entity tb_if02 is
+end tb_if02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_if02 is
+  signal i, o: std_logic_vector(7 downto 0);
+  signal s : std_logic;
+begin
+  dut: entity work.if02
+    port map (i, s, o);
+
+  process
+  begin
+    i <= b"01011010";
+    s <= '0';
+    wait for 1 ns;
+    assert o = x"2d" severity failure;
+
+    i <= b"01011010";
+    s <= '1';
+    wait for 1 ns;
+    assert o = x"b4" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/if01/testsuite.sh b/testsuite/synth/if01/testsuite.sh
index 061e1924a..cb7a8bdf6 100755
--- a/testsuite/synth/if01/testsuite.sh
+++ b/testsuite/synth/if01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in if01; do
+for t in if01 if02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean