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author | Tristan Gingold <tgingold@free.fr> | 2019-09-28 07:23:19 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-28 07:23:19 +0200 |
commit | 4670aa3c0f4f9be576abba68daa17f2667599524 (patch) | |
tree | 5e7527e514c340f20164ba2af0a00412ea2030f7 /testsuite/synth/if01/tb_if01.vhdl | |
parent | 563d56b60c08d70fc30277f26b8f7fc1628b4fe9 (diff) | |
download | ghdl-4670aa3c0f4f9be576abba68daa17f2667599524.tar.gz ghdl-4670aa3c0f4f9be576abba68daa17f2667599524.tar.bz2 ghdl-4670aa3c0f4f9be576abba68daa17f2667599524.zip |
testsuite/synth: add if01
Diffstat (limited to 'testsuite/synth/if01/tb_if01.vhdl')
-rw-r--r-- | testsuite/synth/if01/tb_if01.vhdl | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/testsuite/synth/if01/tb_if01.vhdl b/testsuite/synth/if01/tb_if01.vhdl new file mode 100644 index 000000000..2c608137d --- /dev/null +++ b/testsuite/synth/if01/tb_if01.vhdl @@ -0,0 +1,38 @@ +entity tb_if01 is +end tb_if01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_if01 is + signal c0, c1 : std_logic; + signal r : std_logic; +begin + dut: entity work.if01 + port map (c0, c1, r); + + process + begin + c0 <= '1'; + c1 <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + c0 <= '0'; + c1 <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + c0 <= '1'; + c1 <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + c0 <= '0'; + c1 <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; |